EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 44

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9880
0x23
0x24
Table 41. Hsync Output Polarity Settings
Hsync Output Polarity Bit
0
1
0x24
Table 42. Vsync Output Polarity Settings
Vsync Output Polarity Bit
0
1
0x24
Table 43. DE Output Polarity Settings
DE Output Polarity Bit
0
1
0x24
Table 44. Field Output Polarity
Select
0
1
7-0
An 8 bit register that sets the duration of the Hsync
output pulse. The leading edge of the Hsync output is
triggered by the internally generated, phase-adjusted
PLL feedback clock. The AD9880 then counts a
number of pixel clocks equal to the value in this
register. This triggers the trailing edge of the Hsync
output, which is also phase-adjusted. The power-up
default is 32.
7
This bit sets the polarity of the Hsync output. Setting
this bit to 0 sets the Hsync output to active low. Setting
this bit to 1 sets the Hsync output to active high.
Power-up default setting is 1.
6
This bit sets the polarity of the Vsync output (both
DVI and analog). Setting this bit to 0 sets the Vsync
output to active low. Setting this bit to 1 sets the Vsync
output to active high. Power-up default is 1.
5
This bit sets the polarity of the display enable (DE) for
both DVI and analog.
The power-up default is 1.
4
This bit sets the polarity of the field output signal on
Pin 21. The power-up default setting is 1.
Output field polarity (both DVI and analog)
0 = active low out
1 = active high out
The power-up default is 1.
Result
Active low = even field; active high = odd field
Active low = odd field; active high = even field
Hsync Duration
Hsync Output Polarity
Vsync Output Polarity
Display Enable Output Polarity
Field Output Polarity
Result
Hsync output polarity negative
Hsync output polarity positive
Result
Vsync output polarity is negative
Vsync output polarity is positive
Result
DE output polarity is negative
DE output polarity is positive
Rev. 0 | Page 44 of 64
0x24
Table 45. SOGOUT Polarity Settings
SOGOUT
0
1
0x24
Table 46. SOGOUT Polarity Settings
SOGOUT Select
00
01
10
11
0x24 0
Table 47. Output Clock Invert
Select
0
1
0x25
3
This bit sets the polarity of the SOGOUT signal
(analog only).
The power-up default setting is 1.
2-1
These register bits control the output on the SOGOUT
pin. Options are the raw SOG from the slicer (this is
the unprocessed SOG signal produced from the sync
slicer), the raw Hsync, the regenerated sync from the
sync filter, which can generate missing syncs because
of coasting or drop-out, or the filtered sync that
excludes extraneous syncs not occurring within the
sync filter window.
The power-up default setting is 11.
This bit allows inversion of the output clock as
specified by Register 0x25, Bits 7 to 6. The power-up
default setting is 0.
7-6
These bits select the clock output on the DATACLK
pin. They include 1/2× clock, a 2× clock, a 90° phase
shifted clock or the normal pixel clock. The power-up
default setting is 01.
Output Clock Invert
SOG Output Polarity
SOG Output Select
Output Clock Select
Function
Raw SOG from sync slicer (SOG0 or SOG1)
Raw Hsync (Hsync0 or Hsync1)
Regenerated sync from sync filter
Hsync to PLL
Result
Noninverted clock
Inverted clock
Result
Active low
Active high