EVAL-AD9880-ABZ Analog Devices Inc, EVAL-AD9880-ABZ Datasheet - Page 45

• Manufacturer Part Number: EVAL-AD9880-ABZ
• Description: Video Input Module Kit AD9880
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9880-ABZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: HDMI Receiver & Analog Interface
• Secondary Attributes: Triple 8-bit 150MSPS ADC's
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 48. Output Clock Select
Select
00
01
10
11
0x25
Table 49. Output Drive Strength
Output Drive
00
01
10
11
0x25
Table 50. Output Mode
Output
Mode
00
01
10
11
0x25
Table 51. Primary Output Enable
Select
0
1
5-4
These two bits select the drive strength for all the
high-speed digital outputs (except VSOUT, A0 and
O/E field). Higher drive strength results in faster
rise/fall times and in general makes it easier to capture
data. Lower drive strength results in slower rise/fall
times and helps to reduce EMI and digitally generated power
supply noise. The power-up default setting is 11.
3-2
These bits choose between four options for the output
mode, one of which is exclusive to an HDMI input.
4:4:4 mode is standard RGB; 4:2:2 mode is YCrCb,
which reduces the number of active output pins from
24 to 16; 4:4:4 double data rate (DDR) output mode;
and the data is RGB mode, but changes on every clock
edge. The power-up default setting is 00.
The power-up default is 00.
1
This bit places the primary output in active or high
impedance mode.
The primary output is designated when using either
4:2:2 or DDR 4:4:4. In these modes, the data on the
red and green output channels is the primary output,
while the output data on the blue channel (DDR
YCrCb) is the secondary output. The power-up
default setting is 1.
Result
Primary output is in high impedance mode
Primary output is enabled
Result
4:4:4 RGB mode
4:2:2 YCrCb mode + DDR 4:2:2 on blue (secondary)
DDR 4:4:4: DDR mode + DDR 4:2:2 on blue
(secondary)
12-bit 4:2:2 (HDMI option only)
½× pixel clock
1× pixel clock
2× pixel clock
90° phase 1× pixel clock
Result
Output Drive Strength
Output Mode
Primary Output Enable
Result
Low output drive strength
Medium low output drive strength
Medium high output drive strength
High output drive strength
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0x25
Table 52. Secondary Output Enable
Select
0
1
0x26
Table 53. Output Three-State
Select
0
1
0x26
Table 54. SOGout Three-State
Select
0
1
0x26
Table 55. SOGOUT Three-State
Select
0
1
0x26
Result
Normal outputs
All outputs (except SOGOUT) in high impedance mode
0
This bit places the secondary output in active or high
impedance mode.
The secondary output is designated when using either
4:2:2 or DDR 4:4:4. In these modes the data on the
blue output channel is the secondary output while the
output data on the red and green channels is the
primary output. Secondary output is always a DDR
YCrCb data mode. The power-up default setting is 0.
7
When enabled, this bit puts all outputs (except
SOGOUT) in a high impedance state. The power-up
default setting is 0.
6
When enabled, this bit allows the SOGOUT pin to be
placed in a high impedance state. The power-up
default setting is 0.
5
When enabled, this bit places the SPDIF audio output
pins in a high impedance state. The power-up default
setting is 0.
4
When enabled, this bit places the I2S output pins in a
high impedance state. The power-up default setting
is 0.
Result
Secondary output is in high impedance mode
Secondary output is enabled
Result
Normal SOG output
SOGOUT pin is in high impedance mode
Result
Normal SPDIF output
SPDIF pins in high impedance mode
Secondary Output Enable
Output Three-State
SOG Three-State
SPDIF Three-State
I2S Three-State
AD9880