FDG8850NZ Fairchild Semiconductor, FDG8850NZ Datasheet
FDG8850NZ
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FDG8850NZ Summary of contents
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... R Thermal Resistance, Junction to Ambient Single operation θJA Package Marking and Ordering Information Device Marking .50 ©2007 Fairchild Semiconductor Corporation FDG8850NZ Rev.B ® MOSFET General Description This dual N-Channel logic level enhancement mode field effect = 0.75A D transistors are produced using Fairchild’s proprietary, high cell = 0 ...
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... R is determined by the user's board design. θJC θJA a. 350°C/W when mounted Scale 1:1 on letter size paper. 2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%. ©2007 Fairchild Semiconductor Corporation FDG8850NZ Rev 25°C unless otherwise noted J Test Conditions I = 250μ 250μ ...
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... PULSE DURATION = 80 μ s DUTY CYCLE = 0.5%MAX 1.76 VDD = 5V 1.32 0. 150 J 0.44 0.00 0.0 0.5 1 GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDG8850NZ Rev 25°C unless otherwise noted J 2 2.0V GS 2.2 1.8 V =1.8V GS 1.4 μ 1.5V GS 0.6 1 ...
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... DS Figure 9. Forward Bias Safe Operating Area 1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.1 0.01 SINGLE PULSE 0.01 0.0001 0.001 ©2007 Fairchild Semiconductor Corporation FDG8850NZ Rev 25°C unless otherwise noted 10V 15V DD 0.8 1.0 1.2 1.4 100 μ s 1ms 10ms ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ ...