PH3120L,115 NXP Semiconductors, PH3120L,115 Datasheet - Page 2

• Manufacturer Part Number: PH3120L,115
• Description: MOSFET N-CH 20V 100A LFPAK
• Manufacturer: NXP Semiconductors
• Series: TrenchMOS™r

Specifications of PH3120L,115

• Package / Case: LFPak-4
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 2.65 mOhm @ 25A, 10V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 100A
• Vgs(th) (max) @ Id: 2V @ 1mA
• Gate Charge (qg) @ Vgs: 48.5nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 4457pF @ 10V
• Power - Max: 62.5W
• Mounting Type: Surface Mount
• Gate Charge Qg: 48.5 nC
• Minimum Operating Temperature: - 55 C
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 2.25 mOhms
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: 20 V
• Continuous Drain Current: 100 A
• Power Dissipation: 62.5 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2178-2; 934057822115; PH3120L T/R

NXP Semiconductors
2. Pinning information
Table 2.
3. Ordering information
Table 3.
4. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
PH3120L_3
Product data sheet
Pin
1
2
3
4
mb
Type number
PH3120L
Symbol
V
V
I
I
P
T
T
Source-drain diode
I
I
Avalanche ruggedness
E
D
DM
S
SM
stg
j
DS
GS
tot
DS(AL)S
Symbol
S
S
S
G
D
Pinning information
Ordering information
Limiting values
Parameter
drain-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive
drain-source avalanche
energy
Package
Name
LFPAK
Description
source
source
source
gate
mounting base; connected to
drain
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Conditions
T
V
see
V
t
T
T
t
V
unclamped; t
p
p
j
mb
mb
GS
GS
GS
≤ 10 µs; pulsed; T
≤ 10 µs; pulsed; T
≥ 25 °C; T
Figure 3
= 25 °C; see
= 25 °C
= 10 V; T
= 10 V; T
= 10 V; T
Rev. 03 — 30 March 2009
j
p
≤ 150 °C
j(init)
mb
mb
= 0.32 ms; R
= 25 °C; see
= 100 °C; see
Figure 2
= 25 °C; I
mb
mb
= 25 °C; see
= 25 °C
Simplified outline
D
GS
= 46.2 A; V
Figure
= 50 Ω
Figure 1
(LFPAK)
SOT669
1 2 3 4
Figure 3
1;
mb
sup
N-channel TrenchMOS logic level FET
≤ 20 V;
Graphic symbol
Min
-
-20
-
-
-
-
-55
-55
-
-
-
G
mbb076
PH3120L
© NXP B.V. 2009. All rights reserved.
Max
20
20
100
76
300
62.5
150
150
52
152
210
SOT669
D
Version
S
Unit
V
V
A
A
A
W
°C
°C
A
A
mJ
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