FQD3P50TM_F085 Fairchild Semiconductor, FQD3P50TM_F085 Datasheet

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FQD3P50TM_F085

Manufacturer Part Number
FQD3P50TM_F085
Description
MOSFET P-CH 500V 2.1A DPAK
Manufacturer
Fairchild Semiconductor
Series
QFET™r
Datasheet

Specifications of FQD3P50TM_F085

Fet Type
MOSFET P-Channel, Metal Oxide
Fet Feature
Standard
Rds On (max) @ Id, Vgs
4.9 Ohm @ 1.05A, 10V
Drain To Source Voltage (vdss)
500V
Current - Continuous Drain (id) @ 25° C
2.1A
Vgs(th) (max) @ Id
5V @ 250µA
Gate Charge (qg) @ Vgs
23nC @ 10V
Input Capacitance (ciss) @ Vds
660pF @ 25V
Power - Max
2.5W
Mounting Type
Surface Mount
Package / Case
DPak, TO-252 (2 leads+tab), SC-63
Configuration
Single
Transistor Polarity
P-Channel
Resistance Drain-source Rds (on)
4.9 Ohms
Forward Transconductance Gfs (max / Min)
2.1 S
Drain-source Breakdown Voltage
- 500 V
Gate-source Breakdown Voltage
+/- 30 V
Continuous Drain Current
- 2.1 A
Power Dissipation
2.5 W
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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©2009 Fairchild Semiconductor Internati
FQD3P50 / FQU3P50
500V P-Channel MOSFET
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic lamp ballast based on complimentary
half bridge.
Absolute Maximum Ratings
Thermal Characteristics
* When mounted on the minimum pad size recommended (PCB Mount)
V
I
I
V
E
I
E
dv/dt
P
T
T
R
R
R
D
DM
AR
J
L
Symbol
DSS
GSS
AS
AR
D
Symbol
, T
JC
JA
JA
STG
G
Drain-Source Voltage
Drain Current
Drain Current
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
Power Dissipation (T
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
S
FQD Series
D-PAK
D
- Continuous (T
- Continuous (T
- Pulsed
- Derate above 25°C
A
C
= 25°C) *
Parameter
= 25°C)
Parameter
G
T
D
C
C
C
= 25°C unless otherwise noted
S
= 25°C)
= 100°C)
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Features
• -2.1A, -500V, R
• Low gate charge ( typical 18 nC)
• Low Crss ( typical 9.5 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant
FQU Series
I-PAK
FQD3P50 / FQU3P50
Typ
--
--
--
DS(on)
-55 to +150
= 4.9
-1.33
-500
-2.1
-8.4
250
-2.1
-4.5
300
5.0
2.5
0.4
50
30
G
@V
! ! ! !
! ! ! !
Max
110
2.5
50
January 2009
GS
QFET
= -10 V
▶ ▶ ▶ ▶
▶ ▶ ▶ ▶
! ! ! !
! ! ! !
D
S
! ! ! !
! ! ! !
● ●
● ●
● ●
● ●
● ●
● ●
▲ ▲ ▲ ▲
▲ ▲ ▲ ▲
Rev. A2, January 2009
Units
W/°C
Units
°C/W
°C/W
°C/W
V/ns
mJ
mJ
°C
°C
W
W
V
A
A
A
V
A
®

Related parts for FQD3P50TM_F085

FQD3P50TM_F085 Summary of contents

Page 1

... Thermal Resistance, Junction-to-Ambient * JA R Thermal Resistance, Junction-to-Ambient JA * When mounted on the minimum pad size recommended (PCB Mount) ©2009 Fairchild Semiconductor Internati Features • -2.1A, -500V, R • Low gate charge ( typical 18 nC) • Low Crss ( typical 9.5 pF) • Fast switching • 100% avalanche tested • ...

Page 2

... Repetitive Rating : Pulse width limited by maximum junction temperature 102mH -2.1A -50V ≤ -2.7A, di/dt ≤ 200A ≤ DSS, 4. Pulse Test : Pulse width ≤ 300 s, Duty cycle ≤ Essentially independent of operating temperature ©2009 Fairchild Semiconductor International T = 25°C unless otherwise noted C Test Conditions -250 -250 A, Referenced to 25° -500 ...

Page 3

... Drain Current [A] D Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 1200 1000 800 600 400 200 Drain-Source Voltage [V] DS Figure 5. Capacitance Characteristics ©2009 Fairchild Semiconductor International 0 10 ※ Notes : 1. 250μ s Pulse Test 25℃ Figure 2. Transfer Characteristics 0 10 ※ Note : T = 25℃ J ...

Page 4

... Notes : 150 Single Pulse - Drain-Source Voltage [V] DS Figure 9. Maximum Safe Operating Area ©2009 Fairchild Semiconductor International (Continued) 2.5 2.0 1.5 1.0 ※ Notes : 0 -250 μ 0.0 100 150 200 -100 o C] Figure 8. On-Resistance Variation 2.5 2.0 100 1 1.0 0.5 0 Figure 10. Maximum Drain Current ※ ...

Page 5

... Resistive Switching Test Circuit & Waveforms -10V -10V Unclamped Inductive Switching Test Circuit & Waveforms -10V -10V ©2009 Fairchild Semiconductor International Gate Charge Test Circuit & Waveform Same Type Same Type as DUT as DUT -10V -10V DUT DUT DUT DUT ...

Page 6

... Peak Diode Recovery dv/dt Test Circuit & Waveforms Driver ) ( Driver ) DUT ) ( DUT ) DUT ) ( DUT ) ©2009 Fairchild Semiconductor International + + DUT DUT Driver Driver Compliment of DUT Compliment of DUT (N-Channel) (N-Channel) • dv/dt controlled by R • dv/dt controlled by R • I • I controlled by pulse period ...

Page 7

... Mechanical Dimensions TO-252 (DPAK) (FS PKG Code 36) ©2009 Fairchild Semiconductor International 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: millimeters Part Weight per unit (gram): 0.33 Rev. A2, January 2009 ...

Page 8

... Mechanical Dimensions ©2009 Fairchild Semiconductor International I - PAK Dimensions in Millimeters Rev. A2, January 2009 ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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