PHD97NQ03LT,118 NXP Semiconductors, PHD97NQ03LT,118 Datasheet - Page 2

• Manufacturer Part Number: PHD97NQ03LT,118
• Description: MOSFET N-CH TRENCH 25V SOT428
• Manufacturer: NXP Semiconductors
• Series: TrenchMOS™r

Specifications of PHD97NQ03LT,118

• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 6.3 mOhm @ 25A, 10V
• Drain To Source Voltage (vdss): 25V
• Current - Continuous Drain (id) @ 25° C: 75A
• Vgs(th) (max) @ Id: 2.15V @ 1mA
• Gate Charge (qg) @ Vgs: 11.7nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 1570pF @ 12V
• Power - Max: 107W
• Mounting Type: Surface Mount
• Minimum Operating Temperature: - 55 C
• Configuration: Single
• Transistor Polarity: NPN
• Mounting Style: SMD/SMT
• Power Dissipation: 107 W
• Maximum Operating Temperature: + 175 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 934061139118

NXP Semiconductors
2. Pinning information
Table 2.
3. Ordering information
Table 3.
4. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
PHD97NQ03LT_1
Product data sheet
Pin
1
2
3
mb
Type number
PHD97NQ03LT
Symbol
V
V
V
I
I
P
T
T
Source-drain diode
I
I
Avalanche ruggedness
E
D
DM
S
SM
stg
j
DS
DGR
GS
tot
DS(AL)S
Symbol
G
D
S
D
Pinning information
Ordering information
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive
drain-source avalanche
energy
Package
Name
SC-63; DPAK
Description
gate
drain
source
mounting base; connected to
drain
Conditions
T
T
V
V
t
T
T
t
V
unclamped; t
p
p
j
j
mb
mb
GS
GS
GS
≤ 10 µs; pulsed; T
≤ 10 µs; pulsed; T
≥ 25 °C; T
≥ 25 °C; T
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
= 25 °C; see
= 25 °C
= 10 V; T
= 10 V; T
= 10 V; T
Rev. 01 — 24 March 2009
j
j
p
≤ 175 °C
≤ 175 °C; R
mb
mb
j(init)
= 0.1 ms; R
= 100 °C; see
= 25 °C; see
Figure 2
= 25 °C; I
mb
mb
= 25 °C; see
= 25 °C
Simplified outline
GS
GS
D
= 20 kΩ
= 50 Ω
= 35 A; V
Figure
(SC-63; DPAK)
Figure 1
SOT428
1
Figure 3
1; see
mb
2
sup
N-channel TrenchMOS logic level FET
3
≤ 25 V;
Figure 3
PHD97NQ03LT
Graphic symbol
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
G
mbb076
© NXP B.V. 2009. All rights reserved.
Max
25
25
20
69
75
300
107
175
175
75
240
60
Version
SOT428
D
S
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
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