PHD97NQ03LT,118 NXP Semiconductors, PHD97NQ03LT,118 Datasheet - Page 5

• Manufacturer Part Number: PHD97NQ03LT,118
• Description: MOSFET N-CH TRENCH 25V SOT428
• Manufacturer: NXP Semiconductors
• Series: TrenchMOS™r

Specifications of PHD97NQ03LT,118

• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 6.3 mOhm @ 25A, 10V
• Drain To Source Voltage (vdss): 25V
• Current - Continuous Drain (id) @ 25° C: 75A
• Vgs(th) (max) @ Id: 2.15V @ 1mA
• Gate Charge (qg) @ Vgs: 11.7nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 1570pF @ 12V
• Power - Max: 107W
• Mounting Type: Surface Mount
• Minimum Operating Temperature: - 55 C
• Configuration: Single
• Transistor Polarity: NPN
• Mounting Style: SMD/SMT
• Power Dissipation: 107 W
• Maximum Operating Temperature: + 175 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 934061139118

NXP Semiconductors
6. Characteristics
Table 6.
PHD97NQ03LT_1
Product data sheet
Symbol
Static characteristics
V
V
I
I
R
I
R
Dynamic characteristics
Q
Q
Q
Q
Q
V
C
C
C
DSS
GSS
DSS
(BR)DSS
GS(th)
GS(pl)
DSon
G
iss
oss
rss
G(tot)
GS
GS1
GS2
GD
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
drain leakage current
gate leakage current
drain-source on-state
resistance
drain leakage current
gate resistance
total gate charge
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
Conditions
I
I
I
see
I
see
I
see
V
V
V
V
see
V
see
V
see
V
f = 1 MHz
I
see
I
I
see
I
Figure 10
V
T
V
T
V
T
D
D
D
D
D
D
D
D
D
j
j
j
DS
GS
GS
GS
GS
GS
DS
DS
DS
DS
= 250 µA; V
= 250 µA; V
= 1 mA; V
= 1 mA; V
= 1 mA; V
= 25 A; V
= 0 A; V
= 25 A; V
= 25 A; V
= 25 °C; see
= 25 °C
= 25 °C; see
Figure
Figure 5
Figure 5
Figure
Figure
Figure
Figure
Figure
= 25 V; V
= 25 V; V
= 12 V; V
= 0 V; V
= 12 V; V
= 16 V; V
= -16 V; V
= 10 V; I
= 4.5 V; I
= 10 V; I
DS
5; see
7; see
7; see
7; see
9; see
9; see
DS
DS
DS
Rev. 01 — 24 March 2009
DS
DS
DS
GS
D
D
D
= 0 V; V
GS
GS
GS
GS
DS
GS
GS
DS
= 25 A; T
= 25 A; T
= 12 V; V
= 12 V; V
= 12 V; see
= V
= V
= V
= 25 A; T
Figure 11
Figure 11
= 0 V; f = 1 MHz;
= 0 V; T
= 0 V; T
= 0 V; T
= 0 V; f = 1 MHz;
= 0 V; f = 1 MHz;
= 0 V; T
= 0 V; T
= 0 V; T
Figure 6
Figure 8
Figure 8
Figure 8
Figure 10
Figure 10
GS
GS
GS
; T
; T
; T
GS
j
j
j
j
j
GS
GS
= 4.5 V
j
j
j
j
= 25 °C;
= 175 °C;
= -55 °C;
= 175 °C;
= 25 °C;
j
j
j
= 25 °C
= 25 °C
= 25 °C;
= 175 °C
= 25 °C
= -55 °C
= 25 °C
Figure
= 4.5 V;
= 4.5 V;
9; see
N-channel TrenchMOS logic level FET
PHD97NQ03LT
Min
25
22
1.3
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
-
-
-
10.1
8
5.3
-
1.5
11.7
10.2
6.2
3.4
2.8
1.9
3.1
1570
1800
380
160
© NXP B.V. 2009. All rights reserved.
Max
-
-
2.15
-
2.6
1
100
100
12
10.6
6.3
100
-
-
-
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
µA
nA
nA
mΩ
mΩ
mΩ
µA
Ω
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
pF
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