FDM606P Fairchild Semiconductor, FDM606P Datasheet
FDM606P
Specifications of FDM606P
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FDM606P Summary of contents
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... V DS(ON =25°C unless otherwise noted A Parameter 4.5V 2.5V -1.8V) GS Package Reel Size MicroFET3x2 178 mm December 2004 = -4. -2. -1. Ratings Units - -6.8 A -3.8 A -3.0 A Figure 4 1. 15.4 mW -55 to 150 C o 6.0 C C/W o 208 C/W Tape Width Quantity 8 mm 3000 FDM606P Rev. D2 ...
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... -3.0A, dI /dt = 100A determined by user’s board design copper pad on FR-4. Min Typ Max - 100 100 -0.4 -0.9 -1.5 - 0.026 0.030 - 0.033 0.038 - 0.052 0.070 - 2200 - - 350 - - 160 - - -10V -3. 3 1.0mA 134 - - 308 - -0.9 -1 Units FDM606P Rev. D2 ...
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... C) Figure 2. Maximum Continuous Drain Current RECTANGULAR PULSE DURATION ( -2. PULSE WIDTH (s) Figure 4. Peak Current Capability V = -4. -2. 100 125 CASE TEMPERATURE ( C) A Case Temperature NOTES: DUTY FACTOR PEAK FOR TEMPERATURES o ABOVE 25 C DERATE PEAK CURRENT AS FOLLOWS: 150 - 125 FDM606P Rev. D2 150 ...
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... Figure 10. Normalized Drain to Source Breakdown Voltage vs Junction Temperature = -4. -2. PULSE DURATION = DUTY CYCLE = 0.5% MAX 0.5 1.0 1 DRAIN TO SOURCE VOLTAGE (V) DS PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX V = -4.5V - 120 JUNCTION TEMPERATURE ( 250 120 JUNCTION TEMPERATURE ( -2V = -1.8V 2.0 = -6.8A 160 160 FDM606P Rev. D2 ...
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... Figure 13. Switching Time vs Gate Resistance ©2004 Fairchild Semiconductor Corporation (Continued 25°C unless otherwise noted ISS OSS Figure 12. Gate Charge Waveforms for Constant 400 V = -4.5V -10V -3. 300 200 100 GATE TO SOURCE RESISTANCE ( ) -10V DD WAVEFORMS IN DESCENDING ORDER -6. - GATE CHARGE (nC) g Gate Currents t d(OFF d(ON FDM606P Rev. D2 ...
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... GS I g(REF) Figure 14. Gate charge Test Circuit Figure 16. Switching Time Test Circuit ©2004 Fairchild Semiconductor Corporation DUT g(REF) Figure 15. Gate Charge Waveforms t d(ON DUT 0 10 Figure 17. Switching Time Waveforms -2. g(-2. -4. g(TOT OFF t d(OFF 10% 10% 90% 90% 50% 50% PULSE WIDTH 90% FDM606P Rev. D2 ...
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... 0.041 + Area ©2004 Fairchild Semiconductor Corporation , and the JM 250 , application’s ambient o ( C/W) JA 200 is never exceeded. JM 150 (EQ. 1) 100 50 0.001 is DM Figure 18. Thermal Resistance vs Mounting dissipation. Pulse (EQ 58.9 + 6.8/(0.041+Area) JA 0.01 0 AREA, TOP COPPER AREA (in ) Pad Area FDM606P Rev. D2 ...
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... PSPICE Electrical Model .SUBCKT FDM606P rev Oct. 2001 18.3e- 18.3e-10 CIN 6 8 19.8e-10 DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK -23.4 EDS EGS ESG EVTHRES EVTEMP LGATE GATE LDRAIN 2 5 1e-9 1 LGATE 1 9 1.1e-9 RLGATE LSOURCE 3 7 0.78e-9 ...
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... DPLCAP EVTHRES + 19 EVTEMP LGATE 8 RGATE + RLGATE CIN S1A S2A S1B S2B EDS EGS 8 8 LDRAIN RLDRAIN RSLC1 ISCL EBREAK 18 50 RDRAIN DBODY MWEAK MMED DBREAK MSTRO LSOURCE RSOURCE 8 7 RLSOURCE RBREAK 17 18 RVTEMP 19 IT VBAT + 8 22 RVTHRES FDM606P Rev. D2 DRAIN 2 SOURCE 3 ...
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... RTHERM2 c2 c3 1.3 RTHERM3 c3 c4 2.5 RTHERM4 c4 c5 3.0 RTHERM5 c5 c6 4.0 RTHERM6 c6 c7 7.7 RTHERM7 c7 c8 12.7 RTHERM8 c8 Ambient 24 SABER Thermal Model SABER thermal model FDM606P Copper Area= 1sq.in template thermal_model th tl thermal_c th ctherm.ctherm1 2.0e-4 ctherm.ctherm2 3.0e-4 ctherm.ctherm3 7.0e-4 ctherm.ctherm4 2.0e-3 ctherm ...
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... BSC 1 r1 0.127 BSC Ø All dimensions are in mm. 2. Package outline exclusive of mold flash & metal burr. 3. Package outine inclusive of plating the total number of terminals. 5. Package surface finishing of Ra 0.4 um max. 2.0mm 1.77mm 3.5mm 178mm 17.0mm 13.0mm 60.0mm 13.0mm FDM606P Rev. D2 ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ ...