PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 149

• Manufacturer Part Number: PIC16F721-E/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2
The SSP module, in I
functions except general call support. It provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the I
specifications:
• I
• I
• Start and Stop bit interrupts enabled to support
• Address masking
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin’s data direction bits as inputs in
the appropriate TRIS register. Upon enabling I
mode, the I
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
Data is sampled on the rising edge and shifted out on
the falling edge of the clock. This ensures that the SDA
signal is valid during the SCL high time. The SCL clock
input must have minimum high and low times for proper
operation.
Specifications”.
FIGURE 17-7:
 2010 Microchip Technology Inc.
firmware Master mode
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
SDA
SCL
I
2
C Mode
2
C slew rate limiters in the I/O pads are
Refer
Read
Shift
Clock
MSb
to
2
I
DIAGRAM
2
C mode, implements all slave
SSPMSK Reg
SSPADD Reg
Match Detect
C™ MODE BLOCK
Stop bit Detect
SSPBUF Reg
SSPSR Reg
Section 23.0
Start and
2
C Standard mode
LSb
Write
Addr Match
Internal
Data Bus
“Electrical
2
C
FIGURE 17-8:
The SSP module has six registers for I
They are:
• SSP Control (SSPCON) register
• SSP Status (SSPSTAT) register
• Serial Receive/Transmit Buffer (SSPBUF) register
• SSP Shift Register (SSPSR), not directly
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
17.2.1
Selection of I
SSPCON register set, forces the SCL and SDA pins to
be open drain, provided these pins are programmed as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the output data,
when required, such as for Acknowledge and slave-
transmitter sequences.
accessible
Note:
PIC16F/LF720/721
Master
HARDWARE SETUP
Pull-up
externally to the SCL and SDA pins for
proper operation of the I
SDA
SCL
2
C mode, with the SSPEN bit of the
resistors
V
TYPICAL I
CONNECTIONS
DD
V
DD
must
2
DS41430A-page 149
C™
2
C module.
SDA
SDA
SCL
SCL
(optional)
Slave 1
Slave 2
be
2
C operation.
provided