PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 166

• Manufacturer Part Number: PIC16F721-E/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
18.6
There are conditions when the device should not write
to the program memory. To protect against spurious
writes, various mechanisms have been built in. On
power-up, WREN is cleared. Also, the Power-up Timer
(64 ms duration) prevents program memory writes.
The write initiates sequence and the WREN bit helps
prevent an accidental write during brown-out, power
glitch or software malfunction.
REGISTER 18-1:
DS41430A-page 166
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-1
—
Protection Against Spurious Write
Unimplemented: Read as ‘1’
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Accesses Configuration, user ID and device ID registers
0 = Accesses Flash program
LWLO: Load Write Latches Only bit
1 =
0 =
FREE: Program Flash Erase Enable bit
Unimplemented: Read as ‘0’
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles.
0 = Inhibits programming/erasing of Program Flash and Data EEPROM.
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
0 = Program/erase operation to the Flash is complete and inactive.
RD: Read Control bit
1 = Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set
0 = Does not initiate a program memory read
1 =
0 =
R/W-0/0
CFGS
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
(not cleared) in software).
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
The next WR command does not initiate a write to the PFM; only the program memory
latches are updated.
The next WR command writes a value from EEDATH:EEDATL into program memory latches
and initiates a write to the PFM of all the data stored in the program memory latches.
Perform an program Flash erase operation on the next WR command (cleared by hardware
after completion of erase).
Perform a program Flash write operation on the next WR command.
W = Writable bit
‘1’ = Bit is set
R/W-0/0
LWLO
R/W/HC-0/0
FREE
S = Setable bit, cleared in hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
18.7
When the device is code-protected, the CPU is able to
read and write unscrambled data to the program
memory.
18.8
When the program memory is write-protected, the CPU
can read and execute from the program memory.
The
write-protected can be modified by the CPU using the
PMCON registers, but the protected program memory
cannot be modified using ICSP mode.
U-0
—
portions
Operation During Code-Protect
Operation During Write-Protect
R/W-0/0
WREN
of
program
 2010 Microchip Technology Inc.
x = Bit is unknown
R/S/HC-0/0
WR
memory
R/S/HC-0/0
that
RD
bit 0
are