PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 238

• Manufacturer Part Number: PIC16F721-E/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
Reset................................................................................... 27
Resets
Revision History ................................................................ 233
S
S (Start) bit ........................................................................ 159
SMP bit...................................................................... 147, 159
Software Simulator (MPLAB SIM)..................................... 185
SPBRG.............................................................................. 129
SPBRG Register ................................................................. 18
Special Event Trigger.......................................................... 80
Special Function Registers ................................................. 14
SPI Mode .......................................................................... 145
SSP ................................................................................... 139
SSPADD Register ............................................................... 18
SSPBUF Register ............................................................... 17
SSPCON Register............................................... 17, 146, 158
SSPEN bit ................................................................. 146, 158
SSPM bits ................................................................. 146, 158
SSPOV bit ................................................................. 146, 158
SSPSTAT Register ............................................. 18, 147, 159
STATUS Register................................................................ 21
Synchronous Serial Port Enable bit (SSPEN)........... 146, 158
Synchronous Serial Port Mode Select bits (SSPM) .. 146, 158
T
T1CON Register.......................................................... 17, 104
T1GCON Register............................................................. 105
T2CON Register.................................................. 17, 108, 148
Temperature Indicator Module ............................................ 89
Thermal Considerations .................................................... 194
Time-out Sequence............................................................. 32
Timer0 ................................................................................. 91
DS41430A-page 238
STATUS ...................................................................... 21
T1CON (Timer1 Control)........................................... 104
T1GCON (Timer1 Gate Control) ............................... 105
T2CON ...................................................................... 108
TRISA (Tri-State PORTA) ........................................... 48
TRISB (Tri-State PORTB) ........................................... 57
TRISC (Tri-State PORTC) .......................................... 63
TXSTA (Transmit Status and Control) ...................... 127
WPUB (Weak Pull-up PORTB) ................................... 57
Associated Registers .................................................. 36
Associated Registers ................................................ 148
Typical Master/Slave Connection ............................. 139
I
Master Mode ............................................................. 141
SPI Mode .................................................................. 139
Typical SPI Master/Slave Connection....................... 139
TMR1ON Bit.............................................................. 105
Associated Registers .................................................. 93
Interrupt....................................................................... 93
Operation .............................................................. 91, 96
Specifications ............................................................ 202
2
C Mode ................................................................... 149
Acknowledge..................................................... 150
Addressing ........................................................ 151
Clock Stretching................................................ 156
Clock Synchronization ...................................... 157
Firmware Master Mode ..................................... 156
Hardware Setup ................................................ 149
Multi-Master Mode ............................................ 156
Reception.......................................................... 152
Sleep Operation ................................................ 157
Start/Stop Conditions ........................................ 150
Transmission..................................................... 154
Slave Mode ....................................................... 143
Timer1................................................................................. 95
Timer2
Timers
Timing Diagrams
Timing Parameter Symbology .......................................... 195
Timing Requirements
TMR0 Register.................................................................... 17
Associated registers ................................................. 106
Asynchronous Counter Mode ..................................... 97
Interrupt .................................................................... 100
Modes of Operation .................................................... 96
Module On/Off (TMR1ON Bit)................................... 105
Operation During Sleep ............................................ 100
Prescaler .................................................................... 97
Specifications ........................................................... 202
Timer1 Gate
TMR1H Register ......................................................... 95
TMR1L Register.......................................................... 95
Associated registers ................................................. 108
Timer1
Timer2
A/D Conversion......................................................... 204
A/D Conversion (Sleep Mode) .................................. 205
Asynchronous Reception.......................................... 126
Asynchronous Transmission..................................... 122
Asynchronous Transmission (Back-to-Back)............ 122
Brown-out Reset (BOR)............................................ 200
Brown-out Reset Situations ........................................ 31
CLKOUT and I/O ...................................................... 199
Clock Synchronization .............................................. 157
Clock Timing ............................................................. 196
I
I
I
I
I
INT Pin Interrupt ......................................................... 38
Slave Select Synchronization ................................... 145
SPI Master Mode ...................................................... 142
SPI Master Mode (CKE = 1, SMP = 1) ..................... 207
SPI Mode (Slave Mode with CKE = 0)...................... 144
SPI Mode (Slave Mode with CKE = 1)...................... 144
SPI Slave Mode (CKE = 0) ....................................... 207
SPI Slave Mode (CKE = 1) ....................................... 208
Synchronous Reception (Master Mode, SREN) ....... 135
Synchronous Transmission ...................................... 133
Synchronous Transmission (Through TXEN) ........... 133
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 201
Timer1 Incrementing Edge ....................................... 100
USART Synchronous Receive (Master/Slave) ......... 206
USART Synchronous Transmission (Master/Slave). 205
Wake-up from Interrupt............................................. 170
I
I2C Bus Start/Stop Bits ............................................. 210
SPI Mode .................................................................. 209
2
2
2
2
2
2
C Bus Data............................................................. 210
C Bus Start/Stop Bits ............................................. 209
C Reception (7-bit Address)................................... 152
C Slave Mode with SEN = 0 (Reception,
C Transmission (7-bit Address).............................. 154
C Bus Data............................................................. 211
Reading and Writing ........................................... 97
Selecting Source ................................................ 97
T1CON ............................................................. 104
T1GCON........................................................... 105
T2CON ............................................................. 108
10-bit Address) ................................................. 153
Case 1 ................................................................ 32
Case 2 ................................................................ 33
Case 3 ................................................................ 33
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