PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 40

• Manufacturer Part Number: PIC16F721-E/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
4.5.1
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTB change and
external RA2/INT pin interrupts.
REGISTER 4-1:
DS41430A-page 40
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
GIE
2:
The appropriate bits in the IOCB register must also be set.
TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing TMR0IF bit.
INTCON REGISTER
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
RABIE: PORTA or PORTB Change Interrupt Enable bit
1 = Enables the PORTA or PORTB change interrupt
0 = Disables the PORTA or PORTB change interrupt
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
RABIF: PORTA or PORTB Change Interrupt Flag bit
1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be
0 = None of the PORTA or PORTB general purpose I/O pins have changed state
R/W-0
PEIE
cleared in software)
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TMR0IE
R/W-0
R/W-0
INTE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
RABIE
R/W-0
Note:
(1)
(1)
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
TMR0IF
R/W-0
(2)
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
RABIF
R/W-x
bit 0