PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 56

• Manufacturer Part Number: PIC16F721-E/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
6.2
PORTB is an 8-bit wide, bidirectional port. The
corresponding
(Register
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-2
Reading the PORTB register
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISB register
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 6-2:
DS41430A-page 56
BANKSEL PORTB
CLRF
BANKSEL ANSELB
CLRF
BANKSEL TRISB
MOVLW
MOVWF
Note:
Example 6-2
PORTB and TRISB Registers
6-7). Setting a TRISB bit (= 1) will make the
PORTB
ANSELB ;Make RB<7:4> digital
B’11110000’;Set RB<7:4> as inputs
TRISB
The ANSELB register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
shows how to initialize PORTB.
data
;
;Init PORTB
;
;
(Register
shows how to initialize PORTB.
INITIALIZING PORTB
direction
6-7) controls the PORTB
(Register
register
6-6) reads the
is
TRISB
6.2.1
The ANSELB register
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no affect on digital
output functions. A pin with TRIS clear and ANSELB
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior
instructions on the affected port.
6.2.2
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:4> enable or
disable each pull-up (see
up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RABPU bit of the OPTION
register.
6.2.3
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:4> enable
or disable the interrupt function for each pin. Refer to
Register
disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present value
is compared with the old value latched on the last read
of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt Flag bit (RABIF) in the INTCON
register.
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a)
b)
A mismatch condition will continue to set flag bit RABIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RABIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After these Resets, the RABIF flag will
continue to be set if a mismatch is present.
Note:
Any read or write of PORTB. This will end the
mismatch condition.
Clear the flag bit RABIF.
6-9.
ANSELB REGISTER
WEAK PULL-UPS
INTERRUPT-ON-CHANGE
When a pin change occurs at the same
time as a read operation on PORTB, the
RABIF flag will always be set. If multiple
PORTB pins are configured for the
interrupt-on-change, the user may not be
able to identify which pin changed state.
when
The
interrupt-on-change
executing
 2010 Microchip Technology Inc.
Register
(Register
6-8). Each weak pull-
6-10) is used to
read-modify-write
feature
is