PIC16F721-E/ML Microchip Technology, PIC16F721-E/ML Datasheet - Page 163

• Manufacturer Part Number: PIC16F721-E/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5
A word of the Flash program memory may only be
written to if the word is in an unprotected segment of
memory.
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT<1:0> of the
Configuration Word Register 2. Flash program memory
must be written in 32-word rows. See
more details. A row consists of 32 words with sequen-
tial addresses, with a lower boundary defined by an
address, where PMADR<4:0>= 00000. All row writes to
program memory are done as 32-word erase and one
to 32-word write operations. The write operation is
edge-aligned. Crossing boundaries is not recom-
mended, as the operation will only affect the new
boundary, wrapping the data values at the same time.
Once the write control bit is set, the Program Memory
(PM) controller will immediately write the data. Program
execution is stalled while the write is in progress.
To erase a program memory row, the address of the
row
PMADRH:PMADRL register pair. A row consists of 32
words so, when selecting a row, PMADR<4:0> are
ignored. After the Address has been set up, then the
following sequence of events must be executed:
1.
2.
3.
To write program data, it must first be loaded into the
buffer latches (see
by first writing the destination address to PMADRL and
PMADRH and then writing the data to PMDATA and
PMDATH. After the address and data have been set
up, then the following sequence of events must be exe-
cuted:
1.
2.
3.
All 32 buffer register locations should be written to with
correct data. If less than 32 words are being written to
in the block of 32 words, then a read from the program
memory location(s) not being written to must be
performed. This takes the data from the program
location(s) not being written and loads it into the
PMDATL and PMDATH registers. Then, the sequence
of events to transfer data to the buffer registers must be
executed.
 2010 Microchip Technology Inc.
Set the WREN and FREE control bits of the
PMCON1 register.
Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
Set the WR control bit of the PMCON1 register.
Set the WREN control bit of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
Set the WR control bit of the PMCON1 register.
to
Writing to Flash Program Memory
erase
Figure
must
18-2). This is accomplished
be
loaded
Figure 18-2
into
the
for
When the LWLO bit is ‘1’, the write sequence will only
load the buffer register and will not actually initiate the
write to program Flash:
1.
2.
3.
To transfer data from the buffer registers to the program
memory, the last word to be written should be written to
the PMDATH:PMDATL register pair. Then, the
following sequence of events must be executed:
1.
2.
3.
4.
This is necessary to provide time for the address and to
be provided to the program Flash memory to be put in
the write latches.
No automatic erase occurs upon the initiation of the
write; if the program Flash needs to be erased before
writing, the row (32 words) must be previously erased.
After the “BSF PMCON1, WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. These two instructions will also be forced in
hardware to NOP, but if an ICD break occurs at this
point, the forcing to NOP will be lost.
Note:
Note:
Set the WREN and LWLO bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the write operation.
Clear the LWLO bit of the PMCON1 Register.
Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
Set control bit WR of the PMCON1 register to
begin the write operation.
Two NOP must follow the setting of the WR bit.
PIC16F/LF720/721
Self-write execution to Flash memory can-
not be done while running in low power
PFM and Voltage Regulator modes.
Therefore, executing a self-write will put
the PFM and voltage regulator into High
Power mode for the duration of the
sequence.
An ICD break that occurs during the 55h -
AAh - Set WR bit sequence will interrupt
the timing of the sequence and prevent
the unlock sequence from occurring. In
this case, no write will be initiated, as
there was no operation to complete.
DS41430A-page 163