ISP1505ABS,551 NXP Semiconductors, ISP1505ABS,551 Datasheet - Page 28

• Manufacturer Part Number: ISP1505ABS,551
• Manufacturer: NXP Semiconductors

Specifications of ISP1505ABS,551

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1505A_ISP1505C_3
Product data sheet
Fig 8.
DATA[7:0]
CLOCK
NXT
STP
DIR
AD indicates the address byte, and D indicates the data byte.
Example of register write, register read, extended register write and extended register read
9.6 Register read and write operations
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
register write
TXCMD
immediate
Figure 8
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1505 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1 .
Figure 9
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
D
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register and setting
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b, which drives SE0
on the bus (DP and DM connected to ground through 45 ). The host also sets
OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled
T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE[1:0] as
shown in
a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is
0
.
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
shows register read and write sequences. The ISP1505 supports immediate
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
Table
extended
11.
Rev. 03 — 26 August 2008
TXCMD
(REGR)
register read
immediate
D
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
TXCMD
(EXTW)
register read
extended
AD
D
Figure 9
© NXP B.V. 2008. All rights reserved.
004aaa710
does not
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