ISP1505ABS,551 NXP Semiconductors, ISP1505ABS,551 Datasheet - Page 31

• Manufacturer Part Number: ISP1505ABS,551
• Manufacturer: NXP Semiconductors

Specifications of ISP1505ABS,551

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 15.
ISP1505A_ISP1505C_3
Product data sheet
Parameter name
RXCMD delay (J and K)
RXCMD delay (SE0)
TX start delay
TX end delay (packets)
TX end delay (SOF)
RX start delay
RX end delay
Fig 10. Example of using the ISP1505 to transmit and receive USB data
DATA [ 7:0 ]
CLOCK
NXT
STP
DIR
PHY pipeline delays
9.8.1.1 ISP1505 pipeline delays
9.8.1.2 Allowed link decision time
9.8.1 USB packet timing
9.8 USB packet transmit and receive
An example of a packet transmit and receive is shown in
packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
The ISP1505 delays are shown in
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.2 .
The amount of clock cycles allocated to the link to respond to a received packet and
correctly receive back-to-back packets is given in
values given in
packet sequences and timing are shown in
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.3 .
link sends
TXCMD
TXCMD
High-speed PHY delay
4
4
1 to 2
3 to 4
6 to 9
5 to 6
5 to 6
ISP1505
accepts
TXCMD
Table 16
DATA
the next data;
link sends
ISP1505
Rev. 03 — 26 August 2008
accepts
for correct USB system operation. Examples of high-speed
end of data
link signals
Table
Full-speed PHY delay
4
4 to 6
6 to 10
not applicable
not applicable
not applicable
17 to 18
15. For a detailed description, refer to UTMI+ Low
ULPI bus
ULPI HS USB host and peripheral transceiver
is idle
Figure 11
ISP1505A; ISP1505C
turnaround
asserts DIR,
turnaround
Table
ISP1505
causing
cycle
and
16. Link designs must follow
RXCMD
Figure
(NXT LOW)
Figure
ISP1505
RXCMD
sends
Low-speed PHY delay
4
16 to 18
74 to 75
not applicable
not applicable
not applicable
122 to 123
10. For details on USB
12. For details, refer to
DATA
(NXT HIGH)
USB data
ISP1505
sends
© NXP B.V. 2008. All rights reserved.
turnaround
DIR, causing
turnaround
deasserts
ISP1505
cycle
004aaa705
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