M25PX32-VMF6E NUMONYX, M25PX32-VMF6E Datasheet - Page 11

• Manufacturer Part Number: M25PX32-VMF6E
• Manufacturer: NUMONYX

Specifications of M25PX32-VMF6E

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
•
•
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Standby mode and not transferring data:
•
•
Figure 5.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5
one device is selected at a time, so only one device drives the Serial Data output (DQ1) line
at a time, the other devices are high impedance. Resistors R (represented in
ensure that the M25PX32 is not selected if the Bus Master leaves the S line in the high
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high
impedance at the same time (for example, when the Bus Master is reset), the clock line (C)
must be connected to an external pull-down resistor so that, when all inputs/outputs become
high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S
and C do not become High at the same time, and so, that the t
The typical value of R is 100 kΩ, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
CS3
SPI interface with
(CPOL, CPHA) =
SPI Bus Master
(0, 0) or (1, 1)
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS2 CS1
shows an example of three devices connected to an MCU, on an SPI bus. Only
Bus Master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
C
S
DQ1DQ0
SPI memory
device
W
V
CC
HOLD
V
R
SS
C
S
Figure
DQ1 DQ0
SPI memory
device
W
6, is the clock polarity when the
V
SHCH
HOLD
CC
R
V
SS
requirement is met).
p
(C
C
S
DQ1DQ0
p
SPI memory
= parasitic
device
Figure
W
V
CC
HOLD
5)
AI13725b
V
11/68
V
V
SS
CC
SS