M25PX32-VMF6E NUMONYX, M25PX32-VMF6E Datasheet - Page 30

• Manufacturer Part Number: M25PX32-VMF6E
• Manufacturer: NUMONYX

Specifications of M25PX32-VMF6E

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

6.4.4
6.4.5
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TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1, BP2) bits
to determine if the protected area defined by the Block Protect bits starts from the top or the
bottom of the memory array:
•
•
The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/V
(W/V
Register Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W/V
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Figure 12. Read Status Register (RDSR) instruction sequence and data-out
S
C
DQ0
DQ1
When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits
starts from the top of the memory array (see
When TB is set to ‘1’, the area protected by the Block Protect bits starts from the
bottom of the memory array (see
PP
) signal allow the device to be put in the hardware protected mode (when the Status
PP
sequence
0
High Impedance
) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
1
2
Instruction
3
4
5
6
7
MSB
7
8
Table 3: Protected area
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
Table 3: Protected area
2
1
0
MSB
7
sizes)
6
Status Register Out
5
4
PP
3
) is driven Low). In
sizes)
2
1
0
7
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