M25PX32-VMF6E NUMONYX, M25PX32-VMF6E Datasheet - Page 50

• Manufacturer Part Number: M25PX32-VMF6E
• Manufacturer: NUMONYX

Specifications of M25PX32-VMF6E

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

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Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
•
•
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
than the Power On Reset (POR) threshold voltage, V
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Dual Input Fast
Program (DIFP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR) and Write to Lock Register (WRLR) instructions
until a time delay of t
threshold. However, the correct operation of the device is not guaranteed if, by this time,
V
be sent until the later of:
•
•
These values are specified in
If the time, t
for READ instructions even if the t
After power-up, the device is in the following state:
•
•
•
•
Normal precautions must be taken for supply line decoupling, to stabilize the V
Each device in a system should have the V
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold voltage, V
to any instruction. (The designer needs to be aware that if power-down occurs while a Write,
Program or Erase cycle is in progress, some data corruption may result.)
•
CC
V
V
is still below V
t
t
The device is in the Standby Power mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0)
V
range.
PUW
VSL
CC
SS
PPH
(min) at power-up, and then for a further delay of t
at power-down
after V
after V
must be applied only when V
VSL
, has elapsed, after V
CC
CC
CC
has passed the V
has passed the V
PUW
(min). No Write Status Register, Program or Erase instructions should
CC
has elapsed after the moment that V
WI
drops from the operating voltage, to below the Power On Reset
, all operations are disabled and the device does not respond
Table
CC
) until V
PUW
Section 3: SPI
11.
CC
CC
WI
delay has not yet fully elapsed.
(min) level.
CC
rises above V
threshold
CC
is stable and in the V
CC
reaches the correct value:
line decoupled by a suitable capacitor close
modes.
WI
CC
– all operations are disabled, and
(min), the device can be selected
VSL
CC
CC
rises above the V
min to V
CC
max voltage
CC
CC
supply.
is less
WI