S25FL064A0LMFI001 Spansion Inc., S25FL064A0LMFI001 Datasheet - Page 22

• Manufacturer Part Number: S25FL064A0LMFI001
• Manufacturer: Spansion Inc.

Specifications of S25FL064A0LMFI001

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 9ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 13mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

9.8
February 27, 2009 S25FL064A_00_C4
Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see
SCK
CS#
SCK
SI
CS#
SI
Figure 9.8
Mode 3
Mode 0
MSB
40
7
41
6
42
5
Data Byte 2
and
0
43
4
D a t a
1
Table 9.4 on page
Figure 9.8 Page Program (PP) Command Sequence
44
3
2
Command
2
45
3
1
46
Table 7.1 on page
S h e e t
4
0
47 48 49 50 51 52 53 54 55
5
7
MSB
S25FL064A
6
6
7
5
28.
23 22 21
MSB
8
Data Byte 3
4
9
3
24-Bit Address
10
13).
2
1
3
28
0
2
29
1
30
MSB
0
7
31
MSB
7
6
32
6
5
Data Byte 256
33
5
4
34
Data Byte 1
PP
4
3
35 36 37 38 39
. The Status Register may
3
2
2
1
1
0
0
23