ISP1760BE,557 NXP Semiconductors, ISP1760BE,557 Datasheet - Page 48

• Manufacturer Part Number: ISP1760BE,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760BE,557

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
[1]
Table 49.
[1]
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
DMA Start Address register (address 0344h) bit allocation
8.3.10 DMA Start Address register
R/W
R/W
15
31
23
15
W
W
W
W
0
7
0
0
0
0
7
0
Table 48.
This register defines the start address select for the DMA read and write operations. See
Table 49
Bit
31 to 24
23 to 16
15 to 0
R/W
R/W
14
30
22
14
W
W
W
W
0
6
0
0
0
0
6
0
for the bit allocation.
Edge Interrupt Count register (address 0340h) bit description
Symbol
MIN_WIDTH[7:0]
-
NO_OF_CLK[15:0] Number of Clocks: Count in number of clocks that the edge
R/W
R/W
13
29
21
13
W
W
W
W
0
5
0
0
0
0
5
0
Rev. 04 — 4 February 2008
START_ADDR_DMA[15:8]
START_ADDR_DMA[7:0]
Description
Minimum Width: Indicates the minimum width between two edge
interrupts in SOFs (1 SOF = 125 s). This is not valid for level
interrupts. A count of zero means that interrupts occur as and
when an event occurs.
reserved
interrupt must be kept asserted on the interface. The default IRQ
pulse width is approximately 500 ns.
NO_OF_CLK[15:8]
R/W
R/W
NO_OF_CLK[7:0]
12
28
20
12
W
W
W
W
0
4
0
0
0
0
4
0
reserved
reserved
[1]
[1]
R/W
R/W
11
27
19
11
W
W
W
W
0
3
1
0
0
0
3
0
Embedded Hi-Speed USB host controller
R/W
R/W
10
26
18
10
W
W
W
W
0
2
1
0
0
0
2
0
R/W
R/W
25
17
W
W
W
W
9
0
1
1
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1760
R/W
R/W
47 of 110
24
16
W
W
W
W
8
0
0
1
0
0
8
0
0
0