SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 50

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
11.1.14 HcFmInterval register
Table 66.
Address: Content of the base address register + 30h
[1]
Table 67.
Address: Content of the base address register + 30h
This register contains a 14-bit value that indicates the bit time interval in a frame—that is,
between two consecutive SOFs—and a 15-bit value indicating the full-speed maximum
packet size that the Host Controller may transmit or receive, without causing a scheduling
overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new
value over the present at each SOF. This provides the possibility for the Host Controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset. The bit allocation of the register is given in
Table 68.
Address: Content of the base address register + 34h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
HcDoneHead - Host Controller Done Head register bit allocation
HcDoneHead - Host Controller Done Head register bit description
HcFmInterval - Host Controller Frame Interval register bit allocation
R/W
R/W
R/W
R/W
Symbol
DH[27:0]
reserved
R/W
FIT
31
23
15
31
0
0
0
7
0
0
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
Description
Done Head: When a TD is completed, the Host Controller writes the
content of HcDoneHead to the NextTD field of the TD. The Host
Controller then overwrites the content of HcDoneHead with the
address of this TD. This is set to logic 0 whenever the Host Controller
writes the content of this register to HCCA.
-
DH[3:0]
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
DH[27:20]
DH[19:12]
DH[11:4]
FSMPS[14:8]
Table
R/W
R/W
R/W
R/W
R/W
27
19
11
27
0
0
0
3
0
0
68.
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
reserved
SAF1562
© NXP B.V. 2010. All rights reserved.
R/W
R/W
R/W
R/W
R/W
[1]
25
17
25
0
0
9
0
1
0
0
50 of 121
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0