SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 98

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
19.13.2 Implication
19.13.3 Workaround
19.14.1 Problem description
19.14.2 Implication
19.14.3 Workaround
19.15.1 Problem description
19.15.2 Implication
19.15.3 Workaround
19.14 Erratum 14
19.15 Erratum 15
The root cause issue is described as follows. The SAF1562 has internal mechanism
which will clear any buffer that is locked for 2 successive SOFs. If the SAF1562 cannot
finish writing the buffer to the system memory during this time, the buffer will be cleared.
This condition will lock the SAF1562 state machine out of the idle state. As a result, the
EHCI stops accessing the PCI bus.
This is hardware and system dependent and usually seen on systems which allocate less
PCI bandwidth to the SAF1562.
Allocate a higher priority of PCI bandwidth to the SAF1562.
Setting the multiplier field in the QH for the asynchronous list to a value other than 1
(for example 2 or 3) will cause the HC to stop responding.
According to the Enhanced Host Controller Interface Specification for Universal Serial Bus
Rev. 1.0, the multiplier bits (bits 30 and 31 of Queue Head DWord 2) apply only to the
periodic list. The EHCI core can stop functioning when this field in asynchronous QH is set
to a value other than 1.
The implication is serious.
The EHCI HCD must keep this field at 1. This is applicable only to the asynchronous list.
In the OHCI, sometimes the HcDoneHead register is not properly updated.
In the OHCI, the interrupt and the WDH bit are set but the HC does not immediately
update the HccaDoneHead register (in the system memory) through the PCI. Therefore,
while reading the HccaDoneHead register, you will get the old data, which is incorrect.
The implication is serious.
When a WDH interrupt occurs, do not check the HccaDoneHead value. Instead check the
condition code for all scheduled TDs to determine whether TD has been completed.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
Hi-Speed Universal Serial Bus PCI Host Controller
SAF1562
© NXP B.V. 2010. All rights reserved.
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