JGE7501MC S L8AL Intel, JGE7501MC S L8AL Datasheet
JGE7501MC S L8AL
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... Intel E7501 Chipset Memory Controller Hub (MCH) Datasheet July 2003 Document Number: 251927-002 ...
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... Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ...
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... MCHCFGNS—MCH Configuration Register (D0:F0) ............................. 43 3.5.16 FDHC—Fixed DRAM Hole Control Register (D0:F0) ............................. 43 3.5.17 PAM[6:0]—Programmable Attribute Map Registers (D0:F0).................. 44 3.5.18 DRB[0:7]—DRAM Row Boundary Register (D0:F0) .............................. 46 3.5.19 DRA[3:0]—DRAM Row Attribute Register (D0:F0) ................................ 47 ® Intel E7501 Chipset MCH Datasheet ................................................................................................... 17 ............................................................................................... 29 3 ...
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... DRAM_UELOG_ADD—DRAM First Uncorrectable Memory Error Ad- dress Register (D0:F1)79 3.6.31 DRAM_CELOG_SYNDROME—DRAM First Correctable Memory Error Syndrome Register (D0:F1)79 3.7 Hub Interface_B PCI-to-PCI Bridge Registers (Device 2, Function 0)80 3.7.1 VID—Vendor Identification Register (D2:F0) ......................................... 81 4 ® Intel E7501 Chipset MCH Datasheet ...
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... ISA Hole Memory Space ...................................................................... 112 4.1.4 TSEG SMM Memory Space ................................................................. 112 4.1.5 I/O APIC Memory Space ...................................................................... 113 4.1.6 System Bus Interrupt Memory Space................................................... 113 4.1.7 High SMM Memory Space ................................................................... 113 4.1.8 Device 2 Memory and Prefetchable Memory ....................................... 113 ® Intel E7501 Chipset MCH Datasheet ............................................................................................ 109 5 ...
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... Thermal Characteristics .................................................................................... 129 6.3 Power Characteristics ....................................................................................... 130 6.4 DC Characteristics ............................................................................................ 130 6.4.1 I/O Interface Signal Groupings ............................................................. 130 6.4.2 DC Characteristics at VCC1_2 = 1.2 V ± 5% ....................................... 132 6.4.3 System Bus Interface DC Characteristics ............................................ 133 6.4.4 DDR Interface DC Characteristics........................................................ 134 6 ........................................................................................ 117 .................................................................................... 129 ® Intel E7501 Chipset MCH Datasheet ...
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... MCH Hub Interface_B Signal Package Trace Length Data .................160 7.3.5 MCH Hub Interface_C Signal Package Trace Length Data .................160 7.3.6 MCH Hub Interface_D Signal Package Trace Length Data .................161 8 Testability ..................................................................................................................163 8.1 XORMODE# Usage ..........................................................................................163 8.2 XOR Chains ......................................................................................................164 ® Intel E7501 Chipset MCH Datasheet ............................................................... 139 7 ...
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... DDR Interface Signal Groups............................................................................ 131 6-5 Hub Interface 2.0 (HI_B, HI_C, HI_D) Signal Groups ....................................... 131 6-6 Hub Interface 1.5 (HI_A) Signal Groups ........................................................... 131 6-7 SMBus Signal Group........................................................................................ 131 6-8 Reset and Miscellaneous Signal Group ............................................................ 131 8 ® Intel E7501 Chipset MCH Datasheet ...
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... MCH LPKG Data for DDR Channel B ............................................................... 158 7-6 MCH LPKG Data for Hub Interface_B............................................................... 160 7-7 MCH LPKG Data for Hub Interface_C............................................................... 160 7-8 MCH LPKG Data for Hub Interface_D............................................................... 161 8-1 XOR Chains ......................................................................................................164 ® Intel E7501 Chipset MCH Datasheet 9 ...
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... New definition added to the DRT - DRAM Timing Register Bits 18:16, 001 = 0 clocks Table 6-2, “DC Characteristics Functional Operating Range“ with new parameters for the Intel Table 6-9, “Operating Condition Supply Voltage“ parameters for the Intel Table 6-9, “Operating Condition Supply Voltage“ ...
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... Intel E7501 Chipset MCH Features ■ Processor/Host Bus Support ® — Intel Xeon™ processor with 512-KByte L2 cache, Intel processor with 533 MHz system bus and ® Intel Pentium 1 Mbyte of L2 cache — 400 MHz or 533 MHz system bus (2X address, 4X data) — ...
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... This page is intentionally left blank. ® Intel E7501 Chipset MCH Datasheet ...
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... It is intended to be used with the Intel ® cache and the Intel for the applied-computing market intended to be used with the Intel with one Mbyte of L2 cache. The Intel E7501 chipset consists of three major components: the ® Intel E7501 Chipset Memory Controller Hub (MCH), the Intel (ICH3-S), and the PCI/PCI-X 64-bit Hub 2 ...
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... Reference Documents For the server market, refer to the Intel Compatible Platform Design Guide and your Field Representative for an expanded set of reference documents. For the applied-computing market, refer to the Intel ® Intel E7501 Chipset Platform Design Guide, and contact your field representative for an expanded set of reference documents. ® ...
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... A chipset component interconnect, the hub interface 2.0 (HI2.0), is designed into the Intel E7501 chipset to provide efficient communication between chipset components for high-speed I/O. Each HI2.0 provides 1 ...
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... Introduction ® Figure 1-1. Intel E7501 Chipset MCH Platform Block Diagram SMBus Devices GPIOs LPC I/F Super I/O 1–4 FWHs 10/100 LAN Controller AC'97 2.1 AC '97 Codec(s) USB 1.1, 6 Ports 4 IDE Devices UltraATA/100 16 Processor Processor MCH 16-bit HI 2.0 16-bit HI 2.0 8-bit HI 1.5 ® ...
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... SSTL-2 Note: Certain signals are logically inverted signals. The logic values are the inversion of the electrical values. ® Intel E7501 Chipset MCH Datasheet This pin is driven to its inactive state prior to tri-stating. This applies to some of the HI signals. This pin is weakly driven to its last driven value. ...
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... Interface PUSTRBF_C C PUSTRBS_C HIRCOMP_C HISWNG_C HIVREF_C HI_D[21:20] HI_D[18:0] PSTRBF_D Hub PSTRBS_D Interface PUSTRF_D D PUSTRS_D HIRCOMP_D HISWNG_D HIVREF_D RSTIN# XORMODE# PWRGOOD SMB_CLK Clocks, SMB_DATA Reset, CLK66 Power, VCC1_2 and VCCA1_2 Misc. VCCAHI1_2 VCCACPU1_2 VCC_CPU VCC2_5 VSS ® Intel E7501 Chipset MCH Datasheet ...
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... This allows parity to be high when all the covered signals are high. The MCH may be configured to send an error message to the Intel over HI_A when it detects an error on one of the AP[1:0]# signals. Error: This signal may be connected to the processor MCERR# or IERR# I output signal, depending on system usage ...
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... Deferred response 011 Reserved (not driven by MCH) 100 Hard Failure (not driven by MCH) 101 No data response 110 Implicit Writeback 111 Normal data response Description Data Bits HD[63:48]#, DBI3# HD[47:32]#, DBI2# HD[31:16]#, DBI1# HD[15:0]#, DBI0# ® Intel E7501 Chipset MCH Datasheet ...
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... Analog HXRCOMP HYRCOMP Analog ® Intel E7501 Chipset MCH Datasheet Response Parity: RSP# provides parity protection for the RS[2:0]# signals. O RSP# is always driven by the MCH and must be valid on all clocks. Response parity is correct when there are an even number of low signals (low voltage) in the set consisting of the RS[2:0]# signals and the RSP# signal itself ...
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... DDR Channel A Voltage Reference: The DDR voltage reference. Analog On-Die Termination RCOMP: ODTCOMP provides compensation for I the On-Die termination for the DDR interface on both channels Analog connected to an external pull-down resistor for on-die termination. Description Section 5.5.4. ® Intel E7501 Chipset MCH Datasheet ...
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... CS_B[7:0]# CKE_B RCVEN_B DDRCOMP_B DDRCVO_B DDRVREF_B[3:0] NOTE: Channel B is not active in single-channel mode. ® Intel E7501 Chipset MCH Datasheet Type I/O DDR Channel B Check Bits: These check bits are required to provide ECC support. SSTL-2 I/O DDR Channel B Data Bus: These signals are the DDR data bus that provides the data for the DRAM devices ...
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... CMOS I Compensation for HI_A: This signal is used to calibrate the HI_A I/O buffers. Analog I HI_A Voltage Swing: This signal provides a reference voltage used by the HIRCOMP_A circuit. Analog I HI_A Reference: Reference voltage input for HI_A. Analog Description ® Intel E7501 Chipset MCH Datasheet ...
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... HI_B[18:0] PSTRBF_B PSTRBS_B PUSTRBF_B PUSTRBS_B HIRCOMP_B HISWNG_B HIVREF_B ® Intel E7501 Chipset MCH Datasheet Type I/O HI_B Signals: These are the ECC signals used for connection between the (as/t/s) 16-bit hub and the MCH. CMOS I/O HI_B Signals: These are the signals used for connection between the 16-bit (as/t/s) hub and the MCH ...
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... HI_C. I Compensation for HI_C: This signal is used to calibrate the HI_C I/O buffers. I HI_C Voltage Swing: This signal provides a reference voltage used by the HIRCOMP_C circuit. I HI_C Reference: Reference voltage input for HI_C. Description ® Intel E7501 Chipset MCH Datasheet ...
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... HIRCOMP_D CMOS HISWNG_D Analog HIVREF_D Analog ® Intel E7501 Chipset MCH Datasheet Type I/O HI_D Signals: These are the ECC signals used for connection between the 16-bit hub and the MCH. I/O HI_D Signals: These signals are used for the connection between the 16-bit hub and the MCH ...
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... Power: This pin is a 1.2 V analog power input pin. Power: This pin is a 1.2 V analog power input pin. Power: For the system bus interface. Power: These pins are 2.5 V power input pins for DDR. Ground: Ground pin. Description ® Intel E7501 Chipset MCH Datasheet ...
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... Registers marked as “Reserved” must not be modified by system software. Writes to “Reserved” registers may cause system failure. Reads from “Reserved” registers may return a non-zero value. ® Intel E7501 Chipset MCH Datasheet Register Description Section 3.4, “I/O Mapped Registers” on ...
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... Hub Interface_C PCI-to-PCI Bridge (16-bit PCI2PCI) Hub Interface_C PCI-to-PCI Bridge Error Reporting (16-bit PCI2PCI) Hub Interface_D PCI-to-PCI Bridge (16-bit PCI2PCI) Hub Interface_D PCI-to-PCI Bridge Error Reporting (16-bit PCI2PCI) 30 Description MCH Function Intel Device #, Function # Device 0, Function 0 Device 0, Function 1 Device 2, Function 0 Device 2, Function 1 Device 3, Function 0 ...
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... Note: The MCH supports a variety of connectivity options. When any of the MCH’s hub interfaces (HI_B, HI_C, and HI_D) is disabled, the associated hub interface’s device registers are not visible. Configuration cycles to these registers will return all ones for a read and master abort for a write. ® Intel E7501 Chipset MCH Datasheet Register Description 31 ...
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... Number register, and less than or equal to the value programmed into the corresponding Subordinate Bus Number register, the configuration cycle is targeting a PCI bus downstream of the targeted hub interface. The MCH generates a Type 1 hub interface configuration cycle on the appropriate hub interface. 32 ® Intel E7501 Chipset MCH Datasheet ...
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... CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bit Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O accesses to 31:0 the CONFIG_DATA register are mapped to configuration space using the contents of CONFIG_ADDRESS. ® Intel E7501 Chipset MCH Datasheet 0CF8h Accessed as a DWord 00000000h R/W 32 bits Descriptions 0CFCh ...
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... RO, R/W 00h R/W 00h R/W 00h R/W 00h R/W 00000010h R/W 00440009h R/W 80h RO,R/W 00h R/W 02h RO, R/W, L R/W, R/WC, 38h R/W/L 0800h R/W 03FFh R/W 0000h R/W 0000h R/W 1D1Dh R/W ® Intel E7501 Chipset MCH Datasheet ...
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... E7501 Chipset MCH Datasheet 00–01h 8086h RO 16 Bits Description Vendor Identification (VID). This register field contains the PCI standard identification for Intel, 8086h. 02–03h 254Ch RO 16 Bits Description Device Identification Number (DID). This is a 16-bit value assigned to the MCH Host- HI Bridge Function 0. ...
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... Bus Master Enable (BME). Hardwired to 1. The MCH is always enabled as a master on HI_A. Memory Access Enable (MAE). Hardwired to 1. The MCH always allows access to main memory. I/O Access Enable (IOAE). Hardwired to 0. The MCH does not implement this bit. ® Intel E7501 Chipset MCH Datasheet ...
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... Device 0 error conditions are enabled in the PCICMD registers. Device 0 error flags are read/reset from the PCISTS register. Received Master Abort Status (RMAS). Hardwired to 0. The Intel sends a Master Abort completion. Received Target Abort Status (RTAS). Software clears this bit by writing it. ...
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... Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which the MCH falls. 00h = Host Bridge. 0Bh 06h RO 8 Bits Description Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH. 06h = Bridge device. ® Intel E7501 Chipset MCH Datasheet ...
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... SVID—Subsystem Vendor Identification Register (D0:F0) Address Offset: Default: Access: Size: This value is used to identify the vendor of the subsystem. Default, Bits Access 0000h 15:0 R/WO ® Intel E7501 Chipset MCH Datasheet 0Dh 00h Reserved 8 Bits Description Reserved 0Eh 00h RO 8 Bits Description PCI Header (HDR) ...
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... Subsystem ID (SUBID). This field should be programmed during BIOS initialization. After it has been written once, it becomes read only. 34h 40h RO 8 Bits Description Capabilities Pointer. Pointer to Platform Dependant Capabilities Identification register block, the first of the chain of capabilities. ® Intel E7501 Chipset MCH Datasheet ...
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... Number of Stop Grant Cycles (NSG). These bits indicate the number of Stop Grant transactions expected on the system bus before a Stop Grant Acknowledge packet is ® sent to the Intel ICH3-S. This field is programmed by the BIOS after it has enumerated the processors and before it has enabled Stop Clock generation in the ICH3-S. Once this field has been set, it should not be modified ...
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... HI_B, accesses between 0_FEC8_1000 and 0_FEC8_1FFF are sent to HI_C, accesses between 0_FEC8_2000 and 0_FEC8_2FFF are sent to HI_D MCH forwards accesses to the IOxAPIC regions to the appropriate interface, as specified by the memory and PCI configuration registers. Reserved ® Intel E7501 Chipset MCH Datasheet ...
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... Default, Bits Access 0b 7 R/W 6:0 00h ® Intel E7501 Chipset MCH Datasheet 52–53h 0000h RO, R/W 16 Bits Description Reserved Scrub Complete. BIOS should poll this bit after enabling auto-initialization to determine when all the ECC has been written to the DRAM is good. Note that this bit is set when the scrub unit completes a complete cycle through DRAM, and is only reset by Hard Reset or Power Good reset ...
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... Read Only - All Reads are serviced by DRAM. All Writes are forwarded to HI_A 10 = Write Only - All writes are sent to DRAM. Reads are serviced by HI_A 11 = Normal DRAM operation - All reads and writes are serviced by DRAM Reserved PAM0. Reserved PAM[6:1]. See HIENABLE definition ® Intel E7501 Chipset MCH Datasheet ...
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... PAM2 5:4 WE PAM3 3:2, 7:6 Reserved PAM3 1:0 WE PAM3 5:4 WE PAM4 3:2, 7:6 Reserved PAM4 1:0 WE PAM4 5:4 WE PAM5 3:2, 7:6 Reserved PAM5 1:0 WE PAM5 5:4 WE PAM6 3:2, 7:6 Reserved PAM6 1:0 WE PAM6 5:4 WE ® Intel E7501 Chipset MCH Datasheet rve ...
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... DRAM row boundary address. Even Row (Single Bank) Row Number Address of DRA Row0 60h Row2 62h Row4 64h Row6 66h Odd Row (present if Double Bank) Row Number Address of DRA Row1 61h Row3 63h Row5 65h Row7 67h ® Intel E7501 Chipset MCH Datasheet ...
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... Access 0b 7 R/W 000b 6:4 R R/W 000b 2:0 R/W ® Intel E7501 Chipset MCH Datasheet 70–73h 00h R/W 8 Bits 70h 71h 72h 73h Description Device Width for Odd-numbered Row. This bit defines the width of the DDR-SDRAM devices populated in this row DIMM ...
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... This field controls the number of 100/133 MHz clocks elapsed from RD the Read Command launch on the DDR interface until returned data is set to be driven on the system bus. The following t values are supported. RD 000 = 7 clocks 001 = 6 clocks 010 = 5 clocks Others = Reserved Reserved ® Intel E7501 Chipset MCH Datasheet ...
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... R/W 00b 2:1 R R/W ® Intel E7501 Chipset MCH Datasheet Description DRAM Idle Timer. This field determines the number of clocks the DRAM controller will remain in the idle state before it begins precharging all pages. 000 = Infinite 001 = 0 clocks 011 = 16 DRAM clocks Others = Reserved ...
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... Refresh Disabled 001 = Refresh Enabled. Refresh interval 15.6 µsec 010 = Refresh Enabled. Refresh interval 7.8 µsec 011 = Refresh Enabled. Refresh interval 64 µsec 111 = Refresh Enabled. Refresh interval 64 clocks (fast refresh mode) Others = Reserved ® Intel E7501 Chipset MCH Datasheet ...
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... R/W 6 3:0 R/W ® Intel E7501 Chipset MCH Datasheet Description Reserved Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. 000 Reserved. 001 NOP Command Enable – All processor cycles to DRAM result in a NOP command on the DRAM interface ...
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... PCI. The I/O buffers associated with HI_B will be disabled and tri-stated. Compensation is disabled The configuration space associated with MCH Device 2 is accessible. The I/O buffers are enabled. ® Intel E7501 Chipset MCH Datasheet ...
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... R 010b 2:0 RO ® Intel E7501 Chipset MCH Datasheet 9Dh 02h RO, R/ Bits Description Reserved SMM Space Open (D_OPEN). When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time ...
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... TSEG Enable (TSEG_EN). This bit enables SMRAM memory for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only. ® Intel E7501 Chipset MCH Datasheet ...
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... Bits Access 15:10 00h 3FFh 9:0 R/W ® Intel E7501 Chipset MCH Datasheet C4–C5h 0800h R/W 16 Bits Description Top of Low Memory (TOLM). This register contains the address that corresponds to bits 31:27 of the maximum DRAM memory address that lies below 4 GB. Configuration software should set this value to either the maximum amount of memory in the system or to the minimum address allocated for PCI memory, whichever is smaller ...
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... When the value in this register is less than the value programmed into the Remap Base register, the remap window is disabled. DE–DFh 0000h R/W 16 Bits Description Scratchpad (SCRTCH). These bits are simply R/W storage bits that have no effect on the MCH functionality. ® Intel E7501 Chipset MCH Datasheet ...
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... Bits Access 15:5 0E8h R/W ® Intel E7501 Chipset MCH Datasheet E0–E1h 1D1Dh R/W 16 Bits Description Reserved Device 4, Function 1 Present Present 1 = Not present Device 3, Function 1 Present Present 1 = Not present Device 2, Function 1 Present Present 1 = Not present Reserved Device 0, Function 1 Present. ...
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... R/WC 00h R/WC 00h R/WC 00h R/W 00h R/W 00h R/W 00h R/WC 00h R/WC 00h R/W 00h R/W 00h R/W 00h R/WC 00h R/WC 00h R/W 00h R/W 00h R/W 00000000h RO 00000000h RO 0000h RO ® Intel E7501 Chipset MCH Datasheet ...
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... Intel E7501 Chipset MCH Datasheet 00–01h 8086h Bits Description Vendor Identification Device (VID). This register field contains the PCI standard identification for Intel, 8086h. 02–03h 2541h Bits Description Device Identification Number (DID). This 16-bit value is assigned to the MCH Host-HI Bridge Function 1. ...
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... Function 0 (address offset 04h, bit 8). The MCH does not have a SERR signal. The MCH communicates the SERR condition by sending a SERR message over HI_A to the Intel older design compatibility or in case FERR/NERR is not used. 0 =Disable. A SERR message is not generated by the MCH for Device 0, Function 1 1 =Enable ...
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... Sticky: Access: Size: This register contains the revision number of the MCH Device 0. Default, Bits Access 00h 7:0 RO ® Intel E7501 Chipset MCH Datasheet 06–07h 0000h No R/WC 16 Bits Description Reserved Signaled System Error (SSE). 0 =SERR Not generated by MCH Device 0. 1 =MCH Device 0, Function 1 (FERR/ NERR) generates a SERR message over HI_A for any enabled Device 0, Function 1 error conditions ...
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... Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH. FFh =Non-defined device. Since this function is used for error conditions, it does not fall into any other class. 0Dh 00h No Reserved 8 Bits Description Reserved ® Intel E7501 Chipset MCH Datasheet ...
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... Address Offset: Default: Sticky: Access: Size: This value is used to identify a particular subsystem. Default, Bits Access 0000h 15:0 R/WO ® Intel E7501 Chipset MCH Datasheet 0Eh 00h Bits Description PCI Header (HDR). Reads and writes to this location have no effect. 2C–2Dh 0000h No R/WO ...
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... MCH detected an error on the System Bus. Reserved HI_D Error Detected HI_D interface error MCH detected an error on HI_D. HI_C Error Detected HI_C interface error MCH detected an error on HI_C. HI_B Error Detected HI_B interface error MCH detected an error on HI_B. Reserved ® Intel E7501 Chipset MCH Datasheet ...
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... R/ R/ R/WC 1:0 00b ® Intel E7501 Chipset MCH Datasheet 44–47h 00000000h Yes R/WC 32 Bits Description Reserved DRAM Interface Error Detected DRAM interface error detected The MCH has detected an error on the DRAM interface. HI_A Error Detected HI_A interface error detected. ...
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... HI_A Data Parity Error Detected data parity error detected MCH detected a parity error on a HI_A data transfer. Reserved HI_A Address/Command Parity Error Detected address or command parity error detected MCH detected a parity error on a HI_A address or command. ® Intel E7501 Chipset MCH Datasheet ...
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... R/ R/WC 3:1 000b 0b 0 R/WC ® Intel E7501 Chipset MCH Datasheet 52h 00h Yes R/WC 8 Bits Description Reserved HI_A Target Abort Target Abort on MCH originated HI_A cycle terminated MCH originated HI_A cycle was terminated with a Target Abort. Reserved HI_A Data Parity Error Detected. ...
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... Generate SCI if bit 6 is set in HIA_FERR or HIA_NERR Reserved SCI on HI_A Data Parity Error Detected Enable SCI generation 1 = Generate SCI if bit 4 is set in HIA_FERR or HIA_NERR Reserved SCI on HI_A Data Address/Command Error Detected Enable SCI generation 1 = Generate SCI if bit 0 is set in HIA_FERR or HIA_NERR ® Intel E7501 Chipset MCH Datasheet ...
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... R R/W 3:1 000b 0b 0 R/W ® Intel E7501 Chipset MCH Datasheet 5Ah 00h No R/W 8 Bits Description Reserved SMI on HI_A Target Abort Enable SMI generation 1 = Generate SMI if bit 6 is set in HIA_FERR or HIA_NERR Reserved SMI on HI_A Data Parity Error Detected Enable SMI generation ...
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... Generate SERR if bit 6 is set in HIA_FERR or HIA_NERR Reserved SERR on HI_A Data Parity Error Detected Enable SERR generation 1 = Generate SERR if bit 4 is set in HIA_FERR or HIA_NERR Reserved SEER on HI_A Data Address/Command Error Detected Enable SERR generation 1 = Generate SERR if bit 0 is set in HIA_FERR or HIA_NERR ® Intel E7501 Chipset MCH Datasheet ...
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... R/WC ® Intel E7501 Chipset MCH Datasheet 60h 00h Yes R/WC 8 Bits Description System Bus BINIT# Detected system bus BINIT# detected This bit is set on an electrical high-to-low transition (logical BINIT#. System Bus xERR# Detected system bus XERR# detected This bit is set on an electrical high-to-low transition (logical either IERR# or MCERR# on the system bus ...
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... No System Bus Data Strobe Glitch detected MCH detected a glitch on one of the system bus data strobes. System Bus Request/Address Parity Error (SBRPAR system bus request/address parity error detected MCH detected a parity error on either the address or request signals of the system bus. ® Intel E7501 Chipset MCH Datasheet ...
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... R/W ® Intel E7501 Chipset MCH Datasheet 68h 00h No R/W 8 Bits Description SCI on System Bus BINIT# Detected Enable SCI generation 1 = Generate SCI if bit 7 is set in SYSBUS_FERR or SYSBUS_NERR SCI on System Bus xERR# Detected Enable SCI generation 1 = Generate SCI if bit 6 is set in SYSBUS_FERR or SYSBUS_NERR SCI on Non-DRAM Lock Error Enable ...
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... Generate SMI if bit 2 is set in SYSBUS_FERR or SYSBUS_NERR SMI on System Bus Data Strobe Glitch Detected Enable SMI generation 1 = Generate SMI if bit 1 is set in SYSBUS_FERR or SYSBUS_NERR SMI on System Bus Request/Address Parity Error Enable SMI generation 1 = Generate SMI if bit 0 is set in SYSBUS_FERR or SYSBUS_NERR ® Intel E7501 Chipset MCH Datasheet ...
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... R/W ® Intel E7501 Chipset MCH Datasheet 6Ch 00h No R/W 8 Bits Description SERR on System Bus BINIT# Detected Enable SERR generation 1 = Generate SERR if bit 7 is set in SYSBUS_FERR or SYSBUS_NERR SERR on System Bus xERR# Detected Enable SERR generation 1 = Generate SERR if bit 6 is set in SYSBUS_FERR or SYSBUS_NERR SERR on Non-DRAM Lock Error Enable ...
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... No uncorrectable memory error detected The MCH has detected an ECC error on the memory interface that is not correctable. Correctable Memory Error Detected correctable memory error detected The MCH has detected and corrected an ECC error on the memory interface. ® Intel E7501 Chipset MCH Datasheet ...
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... SMICMD, or SCICMD registers, respectively. Only one message type can be enabled. Default, Bits Access 7:2 000000b R/W ® Intel E7501 Chipset MCH Datasheet 88h 00h No R/W 8 Bits Description Reserved SCI on Multiple-Bit DRAM ECC Error (DMERR) Enable Disable Enable. The MCH generates an SCI when it detects a multiple-bit error reported by the DRAM controller. ...
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... Enable. The MCH generates a SERR when the DRAM controller detects a single- bit error. A0–A3h 00000000h Yes RO 32 Bits Description Reserved CE Address. This field contains address bits 33:12 of the first correctable memory error. The address bits represent a physical address (i.e., they are post translation). Reserved ® Intel E7501 Chipset MCH Datasheet ...
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... DRAM_CELOG_SYNDROME will retain its value for logging purposes. This register is only valid if the flag in DRAM_FERR or DRAM_NERR is set. Default, Bits Access 0000h 15:0 RO ® Intel E7501 Chipset MCH Datasheet B0–B3h 00000000h Yes RO 32 Bits Description Reserved UE Address. This field contains address bits 33:12 of the first uncorrectable memory error ...
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... RO, R/W 00A0h RO, R/WC See register RO description 04h RO 06h RO 00h R/W 01h RO 00h RO 00h R/W 00h R/W 00h Reserved F0h R/W 00h R/W 02A0h RO, R/WC FFF0h R/W 0000h R/W FFF0h RO, R/W 0000h RO, R/W 00h RO, R/W ® Intel E7501 Chipset MCH Datasheet ...
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... Intel E7501 Chipset MCH Datasheet 00–01h 8086h Bits Description Vendor Identification Device (VID). This register field contains the PCI standard identification for Intel, 8086h. 02–03h 2543h Bits Description Device Identification Number (DID). This is a 16-bit value assigned to the MCH Device 2. Register Description ...
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... Enable. Enables the Memory and Prefetchable memory address ranges defined in the MBASE, MLIMIT, PMBASE, and PMLIMIT registers. IO Access Enable (IOAE Disable. All of Device 2’s I/O space is disabled Enable. Enables the I/O address range defined in the IOBASE and IOLIMIT registers. ® Intel E7501 Chipset MCH Datasheet ...
Page 83
... 4:0 00h ® Intel E7501 Chipset MCH Datasheet 06–07h 00A0h No RO, R/WC 16 Bits Description Detected Parity Error (DPE). Hardwired to 0. Parity is not supported on the primary side of this device. Signaled System Error (SSE). This bit is defined for compatibility with legacy designs. The BIOS should not use this bit and instead use the FERR/NERR support in Device 2, Function 1, offset 06h, bit 14 ...
Page 84
... Device 2 of the MCH falls. 04h = PCI-to-PCI bridge. 0Bh 06h Bits Description Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH Device 2. 06h = Bridge device. ® Intel E7501 Chipset MCH Datasheet ...
Page 85
... Size: This register identifies the header layout of the configuration space. Default, Bits Access 01h 7:0 RO ® Intel E7501 Chipset MCH Datasheet 0Dh 00h No R/W 8 Bits Description Scratchpad MLT (NA7:3). These bits return the value with which they are written; however, they have no internal function and are implemented as a scratchpad. ...
Page 86
... HI_B. Since both Bus 0, Device 2 and the PCI-to-PCI bridge on the other end of the hub interface are considered by configuration software to be PCI bridges, this bus number will always correspond to the bus number assigned to HI_B. ® Intel E7501 Chipset MCH Datasheet ...
Page 87
... Access: Size: This register is not implemented. Default, Bits Access 7:0 00h ® Intel E7501 Chipset MCH Datasheet 1Ah 00h No R/W 8 Bits Description Subordinate Bus Number (BUSN). This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the Device 2 bridge ...
Page 88
... Device 2 bridge to HI_B. Reserved 1Dh 00h No R/W 8 Bits Description I/O Address Limit (IOLIMIT). This field corresponds to A[15:12] of the I/O address limit of Device 2. Devices between this upper limit and IOBASE will be passed to HI_B. Reserved ® Intel E7501 Chipset MCH Datasheet ...
Page 89
... 4:0 00h ® Intel E7501 Chipset MCH Datasheet 1E–1Fh 02A0h No RO, R/WC 16 Bits Description Detected Parity Error (DPE). This bit is defined for compatibility with legacy designs. The BIOS should clear this bit in addition to using the FERR/NERR support in Device 2, Function 1, offset 80h/82h, bits [3:0]. ...
Page 90
... Default, Bits Access FFFh 15:4 R/W 3 20–21h FFF0h No R/W 16 Bits Description Memory Address Base (MBASE). These bits correspond to A[31:20] of the lower limit of the memory range that will be passed by the Device 2 bridge to HI_B. Reserved ® Intel E7501 Chipset MCH Datasheet ...
Page 91
... Default, Bits Access 000h 15:4 R/W 3:0 0h ® Intel E7501 Chipset MCH Datasheet 22–23h 0000h No R/W 16 Bits Description Memory Address Limit (MLIMIT). This field corresponds to A[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 2 bridge to HI_B ...
Page 92
... No RO, R/W 16 Bits Description Prefetchable Memory Address Limit (PMLIMIT). This field corresponds to A[31:20] of the upper limit of the address range passed by bridge Device 2 across HI_B. 64bit Addressing Support. Hardwired to 0s. The MCH supports Outbound 64-bit addressing. ® Intel E7501 Chipset MCH Datasheet ...
Page 93
... R R R/W ® Intel E7501 Chipset MCH Datasheet 3Eh 00h No RO, R/W 8 Bits Description Fast Back-to-Back Enable (FB2BEN). Hardwired to 0. The MCH does not generate fast back-to-back cycles as a master on HI_B. Secondary Bus Reset (SRESET). Hardwired to 0. The MCH does not support generation of reset via this bit on the HI_B ...
Page 94
... HI_B Next Error SERR Command SMI Command SCI Command Default Type 8086h RO 2544h RO 0000h RO, R/W 0000h R/WC See register RO description 00h RO FFh RO 00h RO 0000h R/WO 0000h R/WO 00h R/WC 00h R/WC 00h R/W 00h R/W 00h R/W ® Intel E7501 Chipset MCH Datasheet ...
Page 95
... E7501 Chipset MCH Datasheet 00–01h 8086h Bits Yes Description Vendor Identification (VID). This register field contains the PCI standard identification for Intel. 02–03h 2544h Bits Yes Description Device Identification Number (DID). This is a 16-bit value assigned to the MCH Host- HI_B Bridge Function 1. ...
Page 96
... MCH Device 2, Function 1 generates a SERR message over HI_A for any enabled HIB_FERR, HIB_NERR error conditions. Device 2 error conditions are enabled in the PCICMD and SERRCMD2 registers. Device 2 error flags are read/reset from the PCISTS, HIB_NERR or HIB_FERR registers. Reserved ® Intel E7501 Chipset MCH Datasheet ...
Page 97
... SMB Shadowed: This register contains the Sub-Class Code for the MCH Device 2. Default, Bits Access 00h 7:0 RO ® Intel E7501 Chipset MCH Datasheet 08h See table below Bits Yes Description Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification number for the MCH Device 2 ...
Page 98
... MCH Device 2. Since this function is used for error conditions, it does not fall into any other class. FFh = Non-defined device. 0Eh 00h Bits Yes Description PCI Header (HDR). Reads and writes to this location have no effect. ® Intel E7501 Chipset MCH Datasheet ...
Page 99
... Size: SMB Shadowed: This value is used to identify a particular subsystem. Default, Bits Access 0000h 15:0 R/WO ® Intel E7501 Chipset MCH Datasheet 2C–2Dh 0000h No R/WO 16 Bits Yes Description Subsystem Vendor ID (SUBVID). This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes read only. 2E– ...
Page 100
... Reserved MCH Received SERR From HI_B SERR from HI_B detected MCH detected a SERR on Hub Interface_B (e.g., Intel MCH Master Abort on HI_B (HIBMA). MCH did a master abort to a HI_B request Master Abort on HI_B detected MCH detected an invalid address that will be master aborted. This bit is set even when the MCH does not respond with a Master Abort ...
Page 101
... R/WC ® Intel E7501 Chipset MCH Datasheet 82h 00h Yes R/WC 8 Bits Yes Description Reserved MCH Received SERR from HI_B SERR from HI_B received MCH received a SERR from HI_B. MCH Master Abort on HI_B (HIBMA). MCH did a Master Abort to a HI_B Request. ...
Page 102
... Generate SERR if bit 2 is set in HIB_FERR or HIB_NERR SERR on Uncorrectable Error on Header/Address from HI_B Enable SERR generation 1 = Generate SERR if bit 1 is set in HIB_FERR or HIB_NERR SERR on Uncorrectable Error on Data Transfer from HI_B Enable SERR generation 1 = Generate SERR if bit 0 is set in HIB_FERR or HIB_NERR ® Intel E7501 Chipset MCH Datasheet ...
Page 103
... R/W ® Intel E7501 Chipset MCH Datasheet A2h 00h No R/W 8 Bits Description Reserved SMI on MCH Received SERR from HI_B Enable SMI generation 1 = Generate SMI if bit 6 is set in HIB_FERR or HIB_NERR SMI on MCH Master Abort to a HI_B Request Enable SMI generation 1 = Generate SMI if bit 5 is set in HIB_FERR or HIB_NERR SMI on Received Target Abort on HI_B Enable ...
Page 104
... Generate SCI if bit 2 is set in HIB_FERR or HIB_NERR SCI on Uncorrectable Error on Header/Address from HI_B Enable SCI generation 1 = Generate SCI if bit 1 is set in HIB_FERR or HIB_NERR SCI on Uncorrectable Error on Data Transfer from HI_B Enable SCI generation 1 = Generate SCI if bit 0 is set in HIB_FERR or HIB_NERR ® Intel E7501 Chipset MCH Datasheet ...
Page 105
... IOLIMIT 1E–1Fh SEC_STS 20–21h MBASE 22–23h MLIMIT 24–25h PMBASE 26–27h PMLIMIT 3Eh BCTRL ® Intel E7501 Chipset MCH Datasheet Section 3.7 Register Name VID Vendor Identification DID Device Identification PCI Command PCI Status RID Revision Identification Sub-Class Code BCC Base Class Code ...
Page 106
... HI_C First Error HI_C Next Error SERR Command SMI Command SCI Command Default Type 8086h RO 2546h RO 0000h RO, R/W 0000h R/ 00h RO FFh RO 00h RO 0000h R/WO 0000h R/WO 00h R/WC 00h R/WC 00h R/W 00h R/W 00h R/W ® Intel E7501 Chipset MCH Datasheet ...
Page 107
... IOLIMIT 1E–1Fh SEC_STS 20–21h MBASE 22–23h MLIMIT 24–25h PMBASE 26–27h PMLIMIT 3Eh BCTRL ® Intel E7501 Chipset MCH Datasheet Register Name VID Vendor Identification DID Device Identification PCI Command PCI Status RID Revision Identification Sub-Class Code BCC Base Class Code MLT ...
Page 108
... HI_D Next Error SERR Command SMI Command SCI Command Default Type 8086h RO 2548h RO 0000h RO, R/W 0000h R/WC 01h RO 00h RO FFh RO 00h RO 0000h R/WO 0000h R/WO 00h R/WC 00h R/WC 00h R/W 00h R/W 00h R/W ® Intel E7501 Chipset MCH Datasheet ...
Page 109
... DDR SDRAM channels, devices, banks, rows, and columns in different ways depending upon the type of memory being used and on the density or organization of the memory. See Section 5.5 for more information on DDR SDRAM memory. Figure 4-1. System Address Map ® Intel E7501 Chipset MCH Datasheet – gle – – gle – ditio ...
Page 110
... Figure 4-2 shows the segments within the 1_0000_0000 (4 GB) FF00_0000 FEF0_0000 FEE0_0000 FED0_0000 FEC8_0000 FEC0_0000 Top of Low Memory (TOLM) TEM - TSEG 100C_0000 100A_0000 0100_0000 (16 MB) = Main Memory Region 00F0_0000 (15 MB) = Optional Main Memory Region 0010_0000 (1 MB) ® Intel E7501 Chipset MCH Datasheet ...
Page 111
... PAMDC • PAME0 • PAME4 • PAME8 • PAMEC • PAMF0 ® Intel E7501 Chipset MCH Datasheet 0_000C_0000h to 0_000C_3FFFh 0_000C_4000h to 0_000C_7FFFh 0_000C_8000h to 0_000C_BFFFh 0_000C_C000h to 0_000C_FFFFh 0_000D_0000h to 0_000D_3FFFh 0_000D_4000h to 0_000D_7FFFh 0_000D_8000h to 0_000D_BFFFh 0_000D_C000h to 0_000D_FFFFh 0_000E_0000h to 0_000E_3FFFh 0_000E_4000h to 0_000E_7FFFh 0_000E_8000h to 0_000E_BFFFh 0_000E_C000h to 0_000E_FFFFh ...
Page 112
... When the TSEG SMM space is enabled, and an agent attempts a non-SMM access to TSEG space, then the transaction is specially terminated. Hub interface originated accesses are not allowed to SMM space. 112 ® Intel E7501 Chipset MCH Datasheet ...
Page 113
... Note that these registers must be programmed with values that place the HI_B memory space window between the value in the TOLM register and 4 GB. In addition, neither region should overlap with any other fixed or relocatable area of memory. ® Intel E7501 Chipset MCH Datasheet 0_FEC0_0000h to 0_FEC7_FFFFh 0_FEC8_0000h to 0_FEC8_0FFFh ...
Page 114
... The MCH never responds to I/O or configuration cycles initiated on any of the hub interfaces. Hub interface transactions requiring completion are terminated with “master abort” completion packets on the hub interfaces. Hub interface I/O write transactions not requiring completion are dropped. 114 ® Intel E7501 Chipset MCH Datasheet ...
Page 115
... Note that the High system memory space is the same as the Compatible Transaction Address space. • Compatible Transaction Address • High Transaction Address • TSEG Transaction Address ® Intel E7501 Chipset MCH Datasheet Table 4-1 describes three unique address ranges: System Address Map 115 ...
Page 116
... TOLM register. 116 Transaction Address Space (Adr) A0000h to BFFFFh 0FEDA0000h to 0FEDBFFFFh (TOLM–TSEG_SZ) to TOLM Intel System Memory Space (DRAM) A0000h to BFFFFh A0000h to BFFFFh (TOLM–TSEG_SZ) to TOLM ® E7501 Chipset MCH Datasheet ...
Page 117
... HI_B, HI_C, HI_D, or system memory and are subtractively decoded to HI_A if under 16 GB – 64 MB, unless memory reclaim is enabled. The MCH supports the Intel Xeon processor and Intel Pentium M processor subset of the Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for the address and data signals ...
Page 118
... System Bus Interrupt Intel Xeon processors support system bus interrupt delivery. They do not support the APIC serial bus interrupt delivery mechanism. Interrupt-related messages are encoded on the system bus as “Interrupt Message Transactions.” E7501 chipset platform, system bus interrupts can originate from the processor on the system bus or from a downstream device on the hub interface. In the later case the MCH drives the “ ...
Page 119
... MT/s 100 MHz 400 MT/s NOTE: A 266 MT/s DRAM can be used with a processor supporting a 400 MHz system bus, although the memory interface will be operating at 100 MHz, not 133 MHz. ® Intel E7501 Chipset MCH Datasheet System Bus DRAM DRAM BW Clock Transfer/s 4 ...
Page 120
... In the following discussion the term “row” refers to a set of memory devices that are simultaneously selected by a chip select signal. The MCH supports a maximum of eight rows of memory. For the purposes of this discussion, a “side” DIMM is equivalent to a “row” of SDRAM devices. 120 ® Intel E7501 Chipset MCH Datasheet ...
Page 121
... BIOS needs to determine the size and type of memory used for each of the rows of memory to properly configure the MCH memory interface. SMBus Configuration and Access of the Serial Presence Detect Ports For more details, refer to the Intel Memory Register Programming The required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs ...
Page 122
... Meg 13 2048 MB Row 512 Col x 4 bks Meg 13 1024 MB Row 512 Col x 4 bks x 2 122 Table 5-3 for SDRAM devices “0” “0” “0” “0” “0” “0” ® Intel E7501 Chipset MCH Datasheet ...
Page 123
... DQ-DQS Mapping The following table provides the mapping between data bits and the DQS signals. DQ CB_x[7:4] CB_x[3:0] DQ_x[63:60] DQ_x[59:56] DQ_x[55:52] DQ_x[51:48] DQ_x[47:44] DQ_x[43:40] DQ_x[39:36] DQ_x[35:32] DQ_x[31:28] DQ_x[27:24] DQ_x[23:20] DQ_x[19:16] DQ_x[15:12] DQ_x[11:8] DQ_x[7:4] DQ_x[3:0] ® Intel E7501 Chipset MCH Datasheet ...
Page 124
... Read/Write Thermal Management Time (RTMT / WTMT) has expired. 124 3-DIMM Motherboard 4-DIMM Motherboard No connect DIMM3 CK0, CK0# DIMM2 CK0, CK0# DIMM2 CK0, CK0# DIMM1 CK0, CK0# DIMM1 CK0, CK0# DIMM0 CK0, CK0# DIMM0 CK0, CK0# ® Intel E7501 Chipset MCH Datasheet ...
Page 125
... Three lock modes are possible: • Not locked • All bits except the SRTM and SWTM are locked • All bits including SRTM and SWTM are locked ® Intel E7501 Chipset MCH Datasheet Functional Description 125 ...
Page 126
... ICH3-S, MCH, and the processor power planes. The ICH3-S resume well is still powered. • G3 (Mechanical Off): In this state only the RTC well is powered. The system can only reactivate when the power switch can deliver power to the system. 126 ® Intel E7501 Chipset MCH Datasheet ...
Page 127
... The MCH has inputs for a low voltage, differential pair of clocks called HCLKINP and HCLKINN. These pins receive a host clock from the external clock synthesizer. This clock is used by the host interface and system memory logic. ® Figure 5-1. Intel E7501 Chipset-Based System Clocking Diagram CK408B CPU / CPU# (4) ...
Page 128
... Periodically, the unit will scrub one line and then increment the address counter by 64 bytes or one line. A 16-GB memory array would be completely scrubbed in approximately one day. 5.8.3 DRAM Auto-Initialization The DRAM Auto-initialization algorithms initialize memory at reset to ensure that all lines have valid ECC. 128 ® Intel E7501 Chipset MCH Datasheet ...
Page 129
... CC_MCH V Supply Voltage input with respect to VSS TT_AGTL V DDR Buffer Supply Voltage DD_DDR 6.2 Thermal Characteristics ® Consult the Intel E7500/E7501/E7505 Chipset MCH Thermal Design Guidelines for information on thermal characteristics. ® Intel E7501 Chipset MCH Datasheet Parameter Min –55 –0.38 –0.38 – ...
Page 130
... V MCH Core and HI CC 1.525 V AGTL+ I VTT 1.102 V AGTL+ I 2.5 V Vdd DDR dd_DDR NOTES: 1. When using the Intel 2. When using the Intel 6.4 DC Characteristics 6.4.1 I/O Interface Signal Groupings The signal description includes the type of buffer used for the particular signal: • AGTL+ • ...
Page 131
... Table 6-8. Reset and Miscellaneous Signal Group Signal Signal Type Group Miscellaneous (r) CMOS Input ® Intel E7501 Chipset MCH Datasheet Signals DQ_x [63:0], CB_x [7:0], DQS_x [17:0], RCVEN_x BA_x[1:0], CAS_x#, CKE_x, CMDCLK_x[3:0], CMDCLK_x[3:0]#, CS_x[7:0]#, MA_x[12:0], RAS_x#, WE_x# DDRVREF_x[3:0], DDRCVO_x, DDRCOMP_x, ODTCOMP Signals ...
Page 132
... Table 6-9. Operating Condition Supply Voltage Signal Symbol Group VTT (g) Host AGTL+ Termination Voltage VCC2_5 DDR Buffer Voltage VCC1_2 MCH Core Voltage NOTES: ® 1. When using the Intel Xeon™ processor. ® ® 2. When using the Intel Pentium M processor. 132 Parameter Min 1.15 0.997 2.3 1 ...
Page 133
... Host Address and Data Reference HxVREF (d) Voltage HXSWNG, Host Compensation Reference (d) HYSWNG Voltage NOTES: ® 1. When using the Intel Xeon™ processor. ® ® 2. When using the Intel Pentium M processor. Guaranteed by design. ® Intel E7501 Chipset MCH Datasheet Electrical Characteristics Min ...
Page 134
... NOTE: Actual values dependant on termination resistor values and RCOMP strength modes. 134 Parameter Min DVREF_x + 0.150 DVREF_x + 0.310 0 1.9 2.5 2.5 Nom Max Unit DVREF_x V – 0.150 V DVREF_x – 0.310 0 VCC2_5 V 1 – VCC2_5 / 2 V ® Intel E7501 Chipset MCH Datasheet Notes ...
Page 135
... CLK66 Pin Capacitance Clk HIVREF_x (m) Hub Interface Reference Voltage Hub Interface Swing Reference HISWNG_x (m) Voltage HIRCOMP_x (k) Buffer Compensation NOTE Hub Interface ® Intel E7501 Chipset MCH Datasheet Parameter Min – 0.3 HIVREF+0.1 HISWNG – 0.050 – 0.5 45 22.5 2.4 5.0 0.343 24.75 ...
Page 136
... Nom Max Unit Notes HIVREF 0 V – 0.1 1.2 V 0.05 V HISWNG V + 0.050 µA 25 5.0 pF 0.5 pF 5.0 nH Ω Ω 25 27.5 1.2 V 1 8.0 pF 0.35 0.357 V 0.8 V Ω 25 25.25 ® Intel E7501 Chipset MCH Datasheet ...
Page 137
... CMOS Input Low Voltage IL_CMOS C (r) CMOS Pin Capacitance IN_CMOS Vcc_SMBus CMOS Voltage NOTES: 1. Vcc_CMOS refers to the voltage applied to the 3.3 V tolerant input signals ® Intel E7501 Chipset MCH Datasheet Parameter Min – 0.5 2.1 3.135 Parameter Min – 0.5 2.1 3 ...
Page 138
... Electrical Characteristics 138 ® Intel E7501 Chipset MCH Datasheet ...
Page 139
... Ballout Figure 7-1 shows a top view of the ballout footprint. the ballout footprint to list the signal names for each ball. listing organized alphabetically by signal name. ® Intel E7501 Chipset MCH Datasheet Ballout and Package Specifications Figure 7-2 and Figure 7-3 expand the detail of ...
Page 140
... VSS HI_C18 HI_C5 VSS HI_C15 PUSTRBS VCC1_2 HI_C7 HI_C4 VCC1_2 HI_C14 _C PUSTRBF HI_C0 HI_C6 VSS HI_C8 VSS _C HIRCOMP HI_C3 VSS HI_C11 HI_C13 HI_B2 _C VSS HI_C16 HI_C10 VSS HI_C12 HI_B17 VCC1_2 HIVREF_C HI_C9 VSS VCC1_2 HI_B4 ® Intel E7501 Chipset MCH Datasheet ...
Page 141
... HI_B12 HI_B3 VSS HI_B8 HI_B11 VSS HISWNG PUSTRBS VSS HI_B6 VSS _B _B PUSTRBF HI_B5 VSS VCC1_2 HI_B10 ® Intel E7501 Chipset MCH Datasheet VSS VCC2_5 VSS CS_A4# VCC2_5 VSS DQ_A47 DQ_A54 VSS DQS_A15 DQ_A55 DDR DQ_A43 CS_A2# DQS_A6 VSS DQS_A7 VREF_A1 ...
Page 142
... Ballout and Package Specifications Figure 7-3. MCH Ballout (top view 142 ® Intel E7501 Chipset MCH Datasheet ...
Page 143
... CB_B7 CKE_A CKE_B CLK66 CMDCLK_A0 CMDCLK_A0# CMDCLK_A1 CMDCLK_A1# CMDCLK_A2 CMDCLK_A2# CMDCLK_A3 CMDCLK_A3# CMDCLK_B0 CMDCLK_B0# CMDCLK_B1 CMDCLK_B1# ® Intel E7501 Chipset MCH Datasheet Table 7-1. Ballout by Signal Name Ball # Signal Name Ball # Y7 CMDCLK_B2 J26 AJ6 CMDCLK_B2# K25 AK5 CMDCLK_B3 K27 AL31 CMDCLK_B3# ...
Page 144
... DQS_B13 AC30 DQS_B14 AB30 DQS_B15 AD27 DQS_B16 AF28 DQS_B17 Y30 DRDY# Y3 HA3# AA8 HA4# AB1 HA5# AC3 HA6# AD2 HA7# AB6 HA8# AC4 HA9# AD4 HA10# AE5 HA11# AE2 HA12# AC6 HA13# AB9 HA14# AE6 ® Intel E7501 Chipset MCH Datasheet ...
Page 145
... HCLKINN HCLKINP HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# ® Intel E7501 Chipset MCH Datasheet Table 7-1. Ballout by Signal Name Ball # Signal Name Ball # AE3 HD16# F7 AD5 HD17# L7 AB8 HD18# L6 AC7 HD19# E6 ...
Page 146
... PUSTRBF_C D18 PUSTRBS_C E17 PUSTRBF_D B25 PUSTRBS_D C25 PWRGOOD A28 RAS_A# AN24 RAS_B# V32 RCVEN_A AG20 RCVEN_B R25 Reserved AK27 Reserved M25 Reserved E30 Reserved B30 Reserved AM18 Reserved K33 Reserved D29 RS0# V2 RS1# V5 RS2# U4 ® Intel E7501 Chipset MCH Datasheet ...
Page 147
... VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC1_2 ® Intel E7501 Chipset MCH Datasheet Table 7-1. Ballout by Signal Name Ball # Signal Name Ball # AK4 VCC1_2 L20 E28 VCC1_2 L22 J25 VCC1_2 B28 B31 ...
Page 148
... VSS B10 VSS B13 VSS B16 VSS B19 VSS B22 VSS B26 VSS B29 VSS B4 VSS B7 VSS C1 VSS C12 VSS C15 VSS C21 VSS C27 VSS C30 VSS C33 VSS C6 VSS C9 VSS D11 VSS D14 ® Intel E7501 Chipset MCH Datasheet ...
Page 149
... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ® Intel E7501 Chipset MCH Datasheet Table 7-1. Ballout by Signal Name Ball # Signal Name Ball # D17 VSS P2 D20 VSS M3 D23 VSS M9 D31 VSS P8 ...
Page 150
... W16 VSS W18 VSS W20 VSS W24 VSS W28 VSS W31 VSS W33 VSS Y15 VSS Y17 VSS Y19 VSS Y23 VSS Y26 VSS Y32 VSS AJ8 WE_A# AE23 WE_B# D32 XERR# AK2 XORMODE# C29 ® Intel E7501 Chipset MCH Datasheet ...
Page 151
... Solder Resist Opening Detail A (n)x 0.650 ± 0.040 Metal Edge (n)x ∅ 0.790 ± 0.025 (n)x 0.025 Min NOTE: 1. All dimensions are in millimeters. 2. All dimensions and tolerances conform to ANSI Y14.5M-1982. ® Intel E7501 Chipset MCH Datasheet provide the package specifications for the MCH ...
Page 152
... Primary datum —C— and seating plane are defined by the spherical crowns of the solder balls. 4. All dimensions and tolerances conform to ANSI Y14.5M-1982. 152 Die Substrate 1.10 ± 0.10 mm Seating Plane ® Intel E7501 Chipset MCH Datasheet 0.20 –C– See note 3. ...
Page 153
... Chipset Interface Trace Length Compensation In this section, detailed information is given about the internal component package trace lengths to enable trace length compensation. Trace length compensation is required for platform design. These lengths must be considered when matching trace lengths as described in the Intel Processor and Intel ® ...
Page 154
... HDSTBP1# 331.34 HD16# 389.09 HD17# 376.22 HD18# 859.09 HD19# 730.63 HD20# 770.71 HD21# 566.30 HD22# 400.12 HD23# 797.05 HD24# 689.29 HD25# 693.94 HD26# 411.61 HD27# Intel Ball No. L (mils) PKG B6 841.53 B8 738.27 B9 680.98 A9 774.60 A4 953.78 B5 931.65 E8 645.47 B3 1042.71 A5 929.45 C8 732.32 A8 762 ...
Page 155
... HD38# K2 HD39# K1 HD40# N6 HD41# J5 HD42# P9 HD43# M4 HD44# P7 HD45# N7 HD46# R7 HD47# R8 DBI2# L4 ® Intel E7501 Chipset MCH Datasheet Ballout and Package Specifications L (mils) Signal PKG 734.64 HD28# 519.96 HD29# 618.27 HD30# 495.90 HD31# 600.27 DBI1# 876.45 610.31 630.08 630.04 781.73 HDSTBN3# 717.52 HDSTBP3# 714 ...
Page 156
... AH19 516.81 AM21 747.52 AL20 666.30 AH20 535.43 AJ21 630.27 AN21 813.58 AJ19 529.21 AL6 757.56 AH9 572.24 AG10 486.38 AJ9 594.72 AM3 962.48 AM2 985.43 AH10 527.32 AE11 389.01 AL5 795.23 AM4 884.88 ® Intel E7501 Chipset MCH Datasheet ...
Page 157
... DQS_A15 AM7 DQ_A48 AE12 DQ_A49 AH11 DQ_A50 AG11 DQ_A51 AN5 DQ_A52 AG12 DQ_A53 AF12 DQ_A54 AM9 DQ_A55 AM6 ® Intel E7501 Chipset MCH Datasheet Ball No. L (mils) PKG 778.27 DQS_A8 610.59 DQS_A17 479.84 CB_A0 531.53 CB_A1 782.52 CB_A2 752.83 CB_A3 402.91 CB_A4 478 ...
Page 158
... AE33 853.70 AF31 824.01 W25 625.51 AA28 516.10 AD32 749.21 AG33 842.95 W26 341.73 AC31 791.22 AB30 751.49 AA29 684.05 AB33 832.40 V26 408.03 AD31 819.76 Y28 562.60 AB32 810.43 AB29 655.79 V25 700.39 ® Intel E7501 Chipset MCH Datasheet ...
Page 159
... DQ_B48 DQ_B49 DQ_B50 DQ_B51 DQ_B52 DQ_B53 DQ_B54 DQ_B55 DQS_B7 DQS_B16 DQ_B56 DQ_B57 DQ_B58 DQ_B59 DQ_B60 DQ_B61 DQ_B62 DQ_B63 ® Intel E7501 Chipset MCH Datasheet Ball No. L (mils) PKG AE28 628.50 AD27 575.04 Y25 288.31 AB27 450.75 AH32 881.06 AH31 863.46 AC28 532 ...
Page 160
... C11 610.31 HI_B15 J14 268.74 HI_B21 G13 384.96 Signal Ball No. L (mils) PKG D18 513.38 E17 463.42 D19 555.79 A20 717.12 B20 664.29 C19 615.08 B18 649.05 C18 560.35 E18 452.52 F17 378.19 F16 415.04 ® Intel E7501 Chipset MCH Datasheet ...
Page 161
... HI_D0 D28 HI_D1 G25 HI_D2 G26 HI_D3 F26 HI_D4 G24 HI_D5 A27 HI_D6 H24 HI_D7 C26 HI_D20 E27 ® Intel E7501 Chipset MCH Datasheet Ball No. L (mils) PKG 717.68 PUSTRBF_D 730.08 PUSTRBS_D 772.60 HI_D8 562.64 HI_D9 536.77 HI_D10 592.64 HI_D11 513.82 HI_D12 901 ...
Page 162
... Ballout and Package Specifications 162 This page is intentionally left blank. ® Intel E7501 Chipset MCH Datasheet ...
Page 163
... As long as XORMODE# is asserted the MCH is in XOR-test. As soon as XORMODE# is asserted and 2 HCLKINP/HCLKINN cycles have occurred, all the XOR chains are functional. 8. After deasserting XORMODE#, the MCH should be reset before any other testing is done. ® Intel E7501 Chipset MCH Datasheet Input Input ...
Page 164
... DQ_B15 HI_B4 DQS_B1 HI_B17 DQ_B10 HI_B2 DQ_B11 HI_C12 HI_C13 CMDCLK_B3# HI_C21 CMDCLK_B3 PUSTRBF_C CMDCLK_B1# PUSTRBS_C CMDCLK_B1 HI_C9 HI_C15 DQ_B2 HI_C11 Intel Chain #7 Chain #8 HD57# RSP# HD60# HA28# HD62# HA26# HD55# HA19# HD43# HA24# HD41# HA16# HD47# HA12# HD32# HA6# HD36# HA3# ...
Page 165
... CB_B7 DQS_A8 BA_A0 DQS_B8 CB_A3 CB_B3 CB_A0 CB_B2 DQ_A17 DQ_B16 DQ_A16 DQ_B19 DQS_A11 DQS_B11 DQ_A21 DQ_B21 DQ_A20 DQ_B20 ® Intel E7501 Chipset MCH Datasheet Chain #4 Chain #5 Chain #6 DQ_B0 HI_C14 DQS_B9 HI_C10 DQ_B6 HI_C8 DQ_B5 HI_C16 DQ_B7 HI_C6 DQ_B4 HI_C4 DQS_B0 HI_C3 ...
Page 166
... DQS_A2 DQS_B2 DQ_A18 DQ_B18 DQ_A19 DQ_B17 Out = HI_A0 Out = HI_A1 Out = HI_A2 166 Chain #4 Chain #5 Chain #6 HI_D17 HI_D5 SMB_CLK SMB_DATA Out = Out = HI_A3 Out = HI_A4 HI_A5 ® Intel Chain #7 Chain #8 HD5# HD6# HD0# Out = HI_A6 Out = HI_A7 E7501 Chipset MCH Datasheet ...