JGE7501MC S L8AL Intel, JGE7501MC S L8AL Datasheet - Page 163

• Manufacturer Part Number: JGE7501MC S L8AL
• Manufacturer: Intel

Specifications of JGE7501MC S L8AL

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Testability
8.1
Intel
®
Figure 8-1. XOR Test Tree Chain
E7501 Chipset MCH Datasheet
For Automated Test Equipment (ATE) the MCH supports XOR-tree testing. XOR-tree testing
allows board-level interconnections to be tested. An XOR-Tree is a chain of XOR gates, with each
having one input pin or one bi-directional pin (used as an input pin only) connected to it.
XORMODE# Usage
The XORMODE# is a test input. The MCH enters XORMODE# for board level testing. When the
following conditions are met, the MCH will be in XOR-test. If any of the following are not met,
then XOR-test will not be enabled.
1. Assert PWRGD.
2. Assert RSTIN# for 128 clocks beyond the assertion of PWRGD. RSTIN# may be held
3. Deassert RSTIN#.
4. TSTIN# must not be used to put MCH in some test mode. If TSTIN# is used to put MCH in a
5. Assert XORMODE# and hold asserted.
6. The clocks may be held at the 0 or 1 state; or be fully running. Since HCLKINP/HCLKINN is
7. As long as XORMODE# is asserted the MCH is in XOR-test. As soon as XORMODE# is
8. After deasserting XORMODE#, the MCH should be reset before any other testing is done.
VCC1_2
asserted before PWRGD is asserted.
test mode, then a full reset must be done before asserting XORMODE#. It is illegal to run a
TSTIN# test, and then immediately assert XORMODE#, since the TSTIN# test may leave the
MCH in an unknown state.
a differential pair, the 2 clock inputs should be held in opposite states.
asserted and 2 HCLKINP/HCLKINN cycles have occurred, all the XOR chains are functional.
Input
Input
Input
Input
Input
Testability
XOR
Out
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