JGE7501MC S L8AL Intel, JGE7501MC S L8AL Datasheet - Page 29

• Manufacturer Part Number: JGE7501MC S L8AL
• Manufacturer: Intel

Specifications of JGE7501MC S L8AL

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.1
Intel
®
E7501 Chipset MCH Datasheet
The MCH contains two sets of software accessible registers, accessed via the host processor I/O
address space:
The MCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism 1 in the PCI specification.
The MCH internal registers (I/O mapped and configuration registers) are accessible by the host.
The registers can be accessed as Byte (8-bit), Word (16-bit), or DWord (32-bit) quantities, with the
exception of the CONFIG_ADDRESS Register, which can only be accessed as a DWord. All
multi-byte numeric fields use “little-endian” ordering (i.e., lower addresses contain the least
significant parts of the field).
Register Terminology
RO
R/W
R/W/L
R/WC
L
Sticky
Reserved Bits
Reserved
Registers
•
•
Control registers – These registers are I/O mapped into the processor I/O space, which
control access to PCI configuration space (see
page
Internal configuration registers – These registers, which reside within the MCH, are
partitioned into multiple logical device register sets (“logical” since they reside within a single
physical device). One of the register sets is dedicated to Host-HI Bridge functionality (controls
DRAM configuration, other chipset operating parameters, and optional features). Other
register sets map to HI_B, HI_C, and HI_D.
Term
3-33).
Read Only: If a register is read only, writes to this register have no effect.
Read/Write: A register with this attribute can be read and written.
Read/Write/Lock: a register with this attribute can be read, written, and locked.
Read/Write Clear: A register bit with this attribute can be read and written. However, a write
of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Lock: A register bit with this attribute can be written to only once after power-up. After the
first write, the bit becomes read only.
Certain registers in the MCH are sticky through a soft-reset. They will only be reset on a hard
reset or power-good reset. These registers in general are the error logging registers and a
few special cases.
Some of the MCH registers described in this section contain reserved bits. These bits are
labeled “Reserved.” Software must deal correctly with fields that are reserved. On reads,
software must use appropriate masks to extract the defined bits and not rely on reserved bits
being any particular value. On writes, software must ensure that the values of reserved bit
positions are preserved. That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written back. Note that software
does not need to perform read, merge, write operation for the Configuration address
(CONFIG_ADDRESS) register.
The MCH contains address locations in the configuration space of the Host-HI Bridge entity
that are marked “Reserved”. Registers marked as “Reserved” must not be modified by
system software. Writes to “Reserved” registers may cause system failure. Reads from
“Reserved” registers may return a non-zero value.
Section 3.4, “I/O Mapped Registers” on
Description
Register Description
3
29