JGE7501MC S L8AL Intel, JGE7501MC S L8AL Datasheet - Page 20

• Manufacturer Part Number: JGE7501MC S L8AL
• Manufacturer: Intel

Specifications of JGE7501MC S L8AL

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Signal Description
20
Table 2-1. Signal Description (Sheet 2 of 3)
HADSTB[1:0]#
HDSTBP[3:0]#
HDSTBN[3:0]#
Signal Name
HREQ[4:0]#
HD[63:0]#
HA[35:3]#
HLOCK#
HTRDY#
RS[2:0]#
HITM#
HIT#
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2X
2X
4X
4X
2X
O
O
I
Host Address Bus: HA[35:3]# connect to the system address bus. During
processor cycles, HA[35:3]# are inputs. The MCH drives HA[35:3]# whenever it
becomes the system bus master.
Host Address Strobe: The source synchronous strobes are used to transfer
HA[35:3]# and HREQ[4:0]# at the 2X transfer rate.
Strobe
HADSTB0#
HADSTB1#
Host Data: These signals are connected to the system data bus.
Differential Host Data Strobes: The differential source synchronous strobes
are used to transfer HD[63:0]# and DBI[3:0]# at the 4X transfer rate.
Strobe
HDSTBP3#, HDSTBN3#
HDSTBP2#, HDSTBN2#
HDSTBP1#, HDSTBN1#
HDSTBP0#, HDSTBN0#
Hit: HIT# indicates that a caching agent holds an unmodified version of the
requested line. Also, driven in conjunction with HITM# by the target to extend
the snoop window.
Hit Modified: HITM# indicates that a caching agent holds a modified version of
the requested line and that this agent assumes responsibility for providing the
line. HITM# is driven in conjunction with HIT# to extend the snoop window.
Host Lock: This signal indicates to the system that a transaction must occur
atomically. For a locked sequence of transactions, HLOCK# is asserted from the
beginning of the first transaction to the end of the last transaction. When the
priority agent asserts BPRI# to arbitrate for ownership of the processor system
bus, it will wait until it observes HLOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus
locked operation and ensure the atomicity of lock.
Host Request Command: These signals are asserted by the current bus
owner to define the currently active transaction type.
Host Target Ready: This signal indicates that the target of the processor
transaction is able to enter the data transfer phase.
Response Signals: These signals indicate the type of response according to
the following table:
RS[2:0]#
000
001
010
011
100
101
110
111
Response type
Retry response
Idle state
Deferred response
Reserved (not driven by MCH)
Hard Failure (not driven by MCH)
No data response
Implicit Writeback
Normal data response
Address Bits
HA[16:3]#, HREQ[4:0]#
HA[35:17]#
Data Bits
HD[63:48]#, DBI3#
HD[47:32]#, DBI2#
HD[31:16]#, DBI1#
HD[15:0]#, DBI0#
Description
Intel
®
E7501 Chipset MCH Datasheet