JGE7501MC S L8AL Intel, JGE7501MC S L8AL Datasheet - Page 69

• Manufacturer Part Number: JGE7501MC S L8AL
• Manufacturer: Intel

Specifications of JGE7501MC S L8AL

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.6.17
Intel
®
E7501 Chipset MCH Datasheet
SMICMD_HIA—SMI Command Register (D0:F1)
This register determines whether SMI will be generated when the associated flag is set in
HIA_FERR or HIA_NERR. When an error flag is set in the HIA_FERR or HIA_NERR register, it
can generate a SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or SCICMD
registers, respectively. Only one message type can be enabled.
Address Offset:
Default:
Sticky:
Access:
Size:
Bits
3:1
7
6
4
0
5
Default,
Access
000b
R/W
R/W
R/W
0b
0b
0b
0b
0b
Reserved
SMI on HI_A Target Abort Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in HIA_FERR or HIA_NERR
Reserved
SMI on HI_A Data Parity Error Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 4 is set in HIA_FERR or HIA_NERR
Reserved
SMI on HI_A Data Address/Command Error Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in HIA_FERR or HIA_NERR
5Ah
00h
No
R/W
8 Bits
Description
Register Description
69