JGE7501MC S L8AL Intel, JGE7501MC S L8AL Datasheet - Page 74

• Manufacturer Part Number: JGE7501MC S L8AL
• Manufacturer: Intel

Specifications of JGE7501MC S L8AL

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Register Description
3.6.22
74
SMICMD_SYSBUS—SMI Command Register (D0:F1)
This register determines whether SMI will be generated when the associated flag is set in
SYSBUS_FERR or SYSBUS_NERR. When an error flag is set in the SYSBUS_FERR or
SYSBUS_NERR register, it can generate a SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD registers, respectively. Only one message type can be enabled.
Address Offset:
Default:
Sticky:
Access:
Size:
Bits
7
6
4
3
2
1
0
5
Default,
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
0b
SMI on System Bus BINIT# Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 7 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus xERR# Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on Non-DRAM Lock Error Enable.
0 = No SMI generation
1 = Generate SMI if bit 5 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Address Above TOM Enable.
0 = No SMI generation
1 = Generate SMI if bit 4 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Data Parity Error Enable.
0 = No SMI generation
1 = Generate SMI if bit 3 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Address Strobe Glitch Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 2 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Data Strobe Glitch Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 1 is set in SYSBUS_FERR or SYSBUS_NERR
SMI on System Bus Request/Address Parity Error Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in SYSBUS_FERR or SYSBUS_NERR
6Ah
00h
No
R/W
8 Bits
Description
Intel
®
E7501 Chipset MCH Datasheet