MC9S12D64MFUE Freescale, MC9S12D64MFUE Datasheet - Page 16

• Manufacturer Part Number: MC9S12D64MFUE
• Manufacturer: Freescale

Specifications of MC9S12D64MFUE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 49
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 64KB
• Lead Free Status / RoHS Status: Compliant

MC9S12DJ64 Device User Guide — V01.20
Document References
The Device User Guide provides information about the MC9S12DJ64 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes all
the individual Block Guides of the implemented modules. In a effort to reduce redundancy all module
specific information is located only in the respective Block Guide. If applicable, special implementation
details of the module are given in the block description sections of this document.
See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.
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Ports
– The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5,
– The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
– Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DJ64 Block
Pins not available in 80 pin QFP package
– Port H
– Port J[1:0]
– Port K
– Port M[7:6]
– Port P6
– Port S[7:4]
– PAD[15:8] (ATD1 channels)
PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0 (see Table 0-1).
derivative without BDLC (see Table 0-1).
User Guide), if using a derivative without CAN0 (see Table 0-1).
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must
be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at
Base+$026C.
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefor care must be taken not to clear this bit.
PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1
registers!