74F280PCX Fairchild Semiconductor, 74F280PCX Datasheet

74F280PCX

Manufacturer Part Number
74F280PCX
Description
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74F280PCX

Logical Function
Parity Gen/Checker
Logic Family
F
Number Of Elements
1
Number Of Bits
9
Propagation Delay Time
17ns
High Level Output Current
-1mA
Low Level Output Current
20mA
Operating Supply Voltage (typ)
5V
Package Type
PDIP
Operating Temp Range
0C to 70C
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Pin Count
14
Mounting
Through Hole
Operating Temperature Classification
Commercial
Technology
Bipolar
Lead Free Status / RoHS Status
Not Compliant
© 2000 Fairchild Semiconductor Corporation
74F280SC
74F280SJ
74F280PC
74F280
9-Bit Parity Generator/Checker
General Description
The F280 is a high-speed parity generator/checker that
accepts nine bits of input data and detects whether an
even or an odd number of these inputs is HIGH. If an even
number of inputs is HIGH, the Sum Even output is HIGH. If
an odd number is HIGH, the Sum Even output is LOW. The
Sum Odd output is the complement of the Sum Even out-
put.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Order Number
Package Number
IEEE/IEC
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009512
Connection Diagram
Package Description
April 1988
Revised September 2000
www.fairchildsemi.com

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74F280PCX Summary of contents

Page 1

... N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2000 Fairchild Semiconductor Corporation Package Description Connection Diagram DS009512 April 1988 Revised September 2000 www ...

Page 2

Unit Loading/Fan Out Pin Names I –I Data Inputs 0 8 Odd Parity Output O Even Parity Output E Truth Table Number of HIGH Inputs I – HIGH ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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