MM74HC4046MTC Fairchild Semiconductor, MM74HC4046MTC Datasheet - Page 10

• Manufacturer Part Number: MM74HC4046MTC
• Description: IC PHASE LOCK LOOP CMOS 16-TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74HCr
• Type: Phase Lock Loop (PLL)r

Specifications of MM74HC4046MTC

• Pll: No
• Input: CMOS
• Output: 3-State
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 14MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 14MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Detailed Circuit Description
Thus in normal operation V
are fed to the loop filter. This differs from some phase
detectors which supply a current output to the loop filter
and this should be considered in the design. (The CD4046
also provides a voltage.)
Figure 5 shows the state tables for all three comparators.
PHASE COMPARATOR I
This comparator is a simple XOR gate similar to the
74HC86, and its operation is similar to an overdriven bal-
anced modulator. To maximize lock range the input fre-
quencies must have a 50% duty cycle. Typical input and
output waveforms are shown in Figure 4. The output of the
phase detector feeds the loop filter which averages the out-
put voltage. The frequency range upon which the PLL will
lock onto if initially out of lock is defined as the capture
range. The capture range for phase detector I is dependent
on the loop filter employed. The capture range can be as
large as the lock range which is equal to the VCO fre-
quency range.
To see how the detector operates refer to Figure 4. When
two square wave inputs are applied to this comparator, an
output waveform whose duty cycle is dependent on the
phase difference between the two signals results. As the
phase difference increases the output duty cycle increases
and the voltage after the loop filter increases. Thus in order
to achieve lock, when the PLL input frequency increases
the VCO input voltage must increase and the phase differ-
ence between comparator in and signal in will increase. At
an input frequency equal f
this requires the phase detector output to be ground hence
the two input signals must be in phase. When the input fre-
MIN
CC
, the VCO input is at 0V and
and ground voltage levels
FIGURE 4. Typical Phase Comparator I. Waveforms
(Continued)
10
quency is f
phase detector inputs must be 180 out of phase.
The XOR is more susceptible to locking onto harmonics of
the signal input than the digital phase detector II. This can
be seen by noticing that a signal 2 times the VCO fre-
quency results in the same output duty cycle as a signal
equal the VCO frequency. The difference is that the output
frequency of the 2f example is twice that of the other exam-
ple. The loop filter and the VCO range should be designed
to prevent locking on to harmonics.
PHASE COMPARATOR II
This detector is a digital memory network. It consists of four
flip-flops and some gating logic, a three state output and a
phase pulse output as shown in Figure 6. This comparator
acts only on the positive edges of the input signals and is
thus independent of signal duty cycle.
Phase comparator II operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO
output and the signal input positive waveform edges. Fig-
ure 7 shows some typical loop waveforms. First assume
that the signal input phase is leading the comparator input.
This means that the VCO’s frequency must be increased to
bring its leading edge into proper phase alignment. Thus
the phase detector II output is set high. This will cause the
loop filter to charge up the VCO input increasing the VCO
frequency. Once the leading edge of the comparator input
is detected the output goes 3-STATE holding the VCO
input at the loop filter voltage. If the VCO still lags the sig-
nal then the phase detector will again charge up to VCO
input for the time between the leading edges of both wave-
forms.
MAX
then the VCO input must be V
CC
and the