CP82C54-10 Intersil, CP82C54-10 Datasheet - Page 10

• Manufacturer Part Number: CP82C54-10
• Description: IC TIMER PROG CMOS 10MHZ 24-DIP
• Manufacturer: Intersil
• Type: Programmable Timerr

Specifications of CP82C54-10

• Frequency: 10MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

the counters selected by setting their corresponding bits D3,
D2, D1 = 1.
A0, A1 = 11; CS = 0; RD = 1; WR = 0
The read-back command may be used to latch multiple
counter output latches (OL) by setting the COUNT bit D5 = 0
and selecting the desired counter(s). This signal command is
functionally equivalent to several counter latch commands,
one for each counter latched. Each counter’s latched count
is held until it is read (or the counter is reprogrammed). That
counter is automatically unlatched when read, but other
counters remain latched until they are read. If multiple count
read-back commands are issued to the same counter
without reading the count, all but the first are ignored; i.e.,
the count which will be read is the count at the time the first
read-back command was issued.
The read-back command may also be used to latch status
information of selected counter(s) by setting STATUS bit D4
= 0. Status must be latched to be read; status of a counter is
accessed by a read from that counter.
The counter status format is shown in Figure 6. Bits D5
through D0 contain the counter’s programmed Mode exactly
as written in the last Mode Control Word. OUTPUT bit D7
contains the current state of the OUT pin. This allows the
user to monitor the counter’s output via software, possibly
eliminating some hardware from a system.
D5:0=Latch count of selected Counter (s)
D4:0=Latch status of selected Counter(s)
D3:1=Select Counter 2
D2:1=Select Counter 1
D1:1=Select Counter 0
D0:Reserved for future expansion; Must be 0
D7:1=Out pin is 1
D6:1=Null count
D5-D0=Counter programmed mode (See Control Word Formats)
OUTPUT
D7
1
0=Out pin is 0
0=Count available for reading
D7
D6
1
FIGURE 5. READ-BACK COMMAND FORMAT
COUNT
COUNT
NULL
D5
D6
FIGURE 6. STATUS BYTE
STATUS
RW1 RW0
D5
D4
10
D4
CNT 2 CNT 1 CNT 0
D3
M2
D3
D2
D2
M1
D1
M0
D1
BCD
D0
D0
0
82C54
NULL COUNT bit D6 indicates when the last count written to
the counter register (CR) has been loaded into the counting
element (CE). The exact time this happens depends on the
Mode of the counter and is described in the Mode Definitions,
but until the counter is loaded into the counting element (CE),
it can’t be read from the counter. If the count is latched or read
before this time, the count value will not reflect the new count
just written. The operation of Null Count is shown below.
THIS ACTION:
A. Write to the control word register:(1) . . . . Null Count = 1
B. Write to the count register (CR):(2) . . . . . Null Count = 1
C. New count is loaded into CE (CR - CE) . . Null Count = 0
If multiple status latch operations of the counter(s) are
performed without reading the status, all but the first are
ignored; i.e., the status that will be read is the status of the
counter at the time the first status read-back command was
issued.
Both count and status of the selected counter(s) may be
latched simultaneously by setting both COUNT and STATUS
bits D5, D4 = 0. This is functionally the same as issuing two
separate read-back commands at once, and the above
discussions apply here also. Specifically, if multiple count
and/or status read-back commands are issued to the same
counter(s) without any intervening reads, all but the first are
ignored. This is illustrated in Figure 7.
If both count and status of a counter are latched, the first
read operation of that counter will return latched status,
regardless of which was latched first. The next one or two
reads (depending on whether the counter is programmed for
one or two type counts) return latched count. Subsequent
reads return unlatched count.
1. Only the counter specified by the control word will have its
2. If the counter is programmed for two-byte counts (least
null count set to 1. Null count bits of other counters are
unaffected.
significant byte then most significant byte) null count goes
to 1 when the second byte is written.
CAUSES: