X9251US24IZ-2.7 Intersil, X9251US24IZ-2.7 Datasheet - Page 3

• Manufacturer Part Number: X9251US24IZ-2.7
• Description: IC XDCP QUAD 256TAP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9251US24IZ-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
• Set the scale factor and zero point in sensor signal
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
• Set and regulate the DC biasing point in an RF power
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
• Set the operating points in temperature control
• Control the operating point for sensors in industrial
• Trim offset and gain errors in artificial intelligent
comparators and detectors
circuit
Q-factor in filter circuits
conditioning circuits
circuits
communication systems
amplifier in wireless systems
systems
systems
systems
systems
3
X9251
Pinout
Pin Assignments
NOTE:
1. A0 and A1 device address pins must be tied to a logic level.
(SOIC)
6, 19
PIN
10
11
12
13
14
15
16
17
18
20
21
22
23
24
1
2
3
4
5
7
8
9
SYMBOL
HOLD
R
V
R
R
R
SCK
R
R
R
V
R
R
R
R
R
R
R
WP
V
SO
CS
NC
R
R
A0
A1
R
R
SI
WP
W3
CC
W0
W1
W2
SO
NC
SS
W3
W0
CS
H3
H0
H1
H2
A0
CC
L3
L0
L1
L2
H3
H0
L3
L0
(24 LD SOIC/TSSOP)
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
Low Terminal of DCP3
System Supply Voltage
Low Terminal of DCP0
High Terminal of DCP0
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
Hardware Write Protect - active low
Serial Data Input for SPI bus
Device Address for SPI bus. (See Note 1)
Low Terminal of DCP1
High Terminal of DCP1
Wiper Terminal of DCP1
System Ground
Wiper Terminal of DCP2
High Terminal of DCP2
Low Terminal of DCP2
Serial Clock for SPI bus
Device select. Pauses the SPI serial bus.
No Connect
10
11
12
1
2
3
4
5
6
7
8
9
TOP VIEW
X9251
X9251
FUNCTION
24
23
22
21
20
19
18
17
16
15
14
13
HOLD
SCK
R
R
R
NC
V
R
R
R
A1
SI
SS
L2
H2
W2
W1
H1
L1
April 13, 2007
FN8166.5