X9251US24IZ-2.7 Intersil, X9251US24IZ-2.7 Datasheet - Page 8

• Manufacturer Part Number: X9251US24IZ-2.7
• Description: IC XDCP QUAD 256TAP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9251US24IZ-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Increment/Decrement Command
The final command is Increment/Decrement (See Figures 6
and 7). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9251 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
S0
SCK
SI
SCK
SI
CS
CS
ID3 ID2 ID1 ID0
ID3 ID2 ID1 ID0
0
0
SCK
DEVICE ID
DEVICE ID
CS
SI
1
1
0
0
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
1
1
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
ID3 ID2 ID1 ID0
0
0
0
0
0
8
DEVICE ID
0
0
0
0
1
INTERNAL
ADDRESS
INTERNAL
ADDRESS
A1 A0
A1 A0
0
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
1
0
0
I3
I3
INSTRUCTION
INSTRUCTION
0
I2
0
OPCODE
OPCODE
I2
INTERNAL
ADDRESS
A1
I1
I1
A0
X9251
I0
I0
REGISTER
ADDRESS
REGISTER
ADDRESS
I3
RB RA
RB RA
INSTRUCTION
For each SCK clock pulse (t
selected wiper moves one wiper position towards the R
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position towards
the R
timing for this operation are shown. See Instruction format
for more details.
OPCODE
I2
P1
P1
ADDRESS
I1
DCP/WCR
ADDRESS
L
DCP/WCR
terminal. A detailed illustration of the sequence and
P0
P0
I0
REGISTER
ADDRESS
RB
D7
D7
X
RA
DATA FOR WCR[7:0] OR DR[7:0]
D6 D5 D4
DATA REGISTER BIT [7:0]
D6 D5 D4
X
P1
ADDRESS
DCP/WCR
X
DON’T CARE
P0
WCR[7:0]
HIGH
X
OR
D3 D2
D3 D2
) while SI is HIGH, the
X
X
D1 D0
X
D1 D0
X
April 13, 2007
FN8166.5
H