X9251US24IZ-2.7 Intersil, X9251US24IZ-2.7 Datasheet - Page 5

• Manufacturer Part Number: X9251US24IZ-2.7
• Description: IC XDCP QUAD 256TAP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9251US24IZ-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

One of Four Potentiometers
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V
potentiometer pins provided that V
positive than or equal to V
V
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.
W
). The V
#: 0, 1, 2, or 3
IF WCR = 00[H] then R
IF WCR = FF[H] then R
CC
FROM INTERFACE
SERIAL DATA PATH
CC
ramp rate specification is always in effect.
CIRCUITRY
and the voltages applied to the
H
, V
W
W
L
5
, and V
is closet to R
is closet to R
CC
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
is always more
W
DR#0
DR#2
(i.e., V
L
H
CC
≥ V
8
H
, V
L
,
X9251
MODIFIED SCK
DR#1
DR#3
UP/DN
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
• When WIP = 0, indicates that no high-voltage write cycle is
8
progress.
in progress.
SERIAL
BUS
INPUT
UP/DN
CLK
PARALLEL
BUS
INPUT
REGISTER
COUNTER
INC/DEC
(WCR#)
LOGIC
WIPER
COUNTER
DECODE
- - -
CORE
DCP
April 13, 2007
R
R
R
H
W
L
FN8166.5