X9251US24IZ-2.7 Intersil, X9251US24IZ-2.7 Datasheet - Page 6

• Manufacturer Part Number: X9251US24IZ-2.7
• Description: IC XDCP QUAD 256TAP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9251US24IZ-2.7

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Interface
The X9251 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in,
on the rising SCK. CS must be LOW and the HOLD and WP
pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
Identification Byte
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the Identification Byte are a
Device Type Identifier, ID[3:0]. For the X9251, this is fixed as
0101 (refer to Table 3).
Data Register Selection
#: 0, 1, 2, or 3
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
REGISTER
WCR7
(MSB)
(MSB)
(MSB)
(MSB)
Bit 7
ID3
I3
0
DR#0
DR#1
DR#2
DR#3
TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE)
WCR6
Bit 6
ID2
I2
1
Device Type
Instruction
Opcode
Identifier
RB
0
0
1
1
6
WCR5
ID1
Bit 5
I1
0
TABLE 3. IDENTIFICATION BYTE FORMAT
TABLE 4. INSTRUCTION BYTE FORMAT
RA
0
1
0
1
ID0
WCR4
I0
Bit 4
1
X9251
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0,
A1 is the logic value at the input pin A1, and A0 is the logic
value at the input pin A0. Only the device which Slave
Address matches the incoming bits sent by the master
executes the instruction. The A1 and A0 inputs can be actively
driven by CMOS input signals or tied to V
Instruction Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below in
Table 4.
RB
A3
WCR3
0
Bit 3
Selection
Register
RA
A2
WCR2
0
Bit 2
Slave Address
Logic Value
Pin A1
A1
P1
WCR1
(WCR Selection)
Bit 1
DCP Selection
CC
Logic Value
or V
Pin A0
(LSB)
(LSB)
A0
P0
SS
WCR0
(LSB)
(LSB)
Bit 0
.
April 13, 2007
FN8166.5