FSDM0365RL_NL Fairchild Semiconductor, FSDM0365RL_NL Datasheet - Page 9

• Manufacturer Part Number: FSDM0365RL_NL
• Manufacturer: Fairchild Semiconductor

Specifications of FSDM0365RL_NL

• Power Switch Family: FSDM0365
• Power Switch On Resistance: 3.6Ohm
• Output Current: 1.89A
• Number Of Outputs: Single
• Mounting: Surface Mount
• Supply Current: 3mA
• Package Type: LSOP
• Operating Temperature (min): -25C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Pin Count: 8
• Power Dissipation: 1.56W
• Lead Free Status / Rohs Status: Compliant

Functional Description
1. Startup : In previous generations of Fairchild Power
Switches (FPS
DC input voltage line. In this generation the startup resistor
is replaced by an internal high voltage current source and a
switch that shuts off when 15ms goes by after the supply
voltage, Vcc, gets above 12V. The source turns back on if
Vcc drops below 8V.
2. Feedback Control : The FSDx0365RN employs current
mode control, as shown in Figure 5. An opto-coupler (such
as the H11A817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network. Com-
paring the feedback voltage with the voltage across the
Rsense resistor plus an offset voltage makes it possible to
control the switching duty cycle. When the KA431 reference
pin voltage exceeds the internal reference voltage of 2.5V,
the optocoupler LED current increases, the feedback voltage
Vfb is pulled down and it reduces the duty cycle. This event
typically happens when the input voltage is increased or the
output load is decreased.
Vo
Figure 5. Pulse Width Modulation (PWM) Circuit
Figure 4. High Voltage Current Source
431
TM
) the Vstr pin had an external resistor to the
Vin,dc
C
Vfb
FB
Vcc
3
V
+
5uA
-
V
FB
Vcc
SD
D1
15ms after
UVLO on
Vcc≥12V
UVLO off
Vcc
Vcc<8V
V
0.9mA
FB,in
D2
2.5R
R
OSC
I
STR
OLP
I
CH
driver
Gate
Vstr
J-FET
3. Leading Edge Blanking (LEB) : At the instant the inter-
nal Sense FET is turned on, the primary side capacitance and
secondary side rectifier diode reverse recovery typically
cause a high current spike through the Sense FET. Excessive
voltage across the Rsense resistor leads to incorrect feedback
operation in the current mode PWM control. To counter this
effect, the FPS employs a leading edge blanking (LEB) cir-
cuit. This circuit inhibits the PWM comparator for a short
time (t
4. Protection Circuits : The FPS has several protective
functions such as over load protection (OLP), over voltage
protection (OVP), abnormal over current protection
(AOCP), under voltage lock out (UVLO) and thermal shut-
down (TSD). Because these protection circuits are fully inte-
grated inside the IC without external components, the
reliability is improved without increasing cost. Once a fault
condition occurs, switching is terminated and the Sense FET
remains off. This causes Vcc to fall. When Vcc reaches the
UVLO stop voltage V
the internal high voltage current source charges the Vcc
capacitor via the Vstr pin. When Vcc reaches the UVLO
start voltage V
operation. In this manner, the auto-restart can alternately
enable and disable the switching of the power Sense FET
until the fault condition is eliminated.
4.1 Over Load Protection (OLP) : Overload is defined as
the load current exceeding a pre-set level due to an unex-
pected event. In this situation, the protection circuit should
be activated in order to protect the SMPS. However, even
when the SMPS is operating normally, the over load protec-
tion (OLP) circuit can be activated during the load transition.
In order to avoid this undesired operation, the OLP circuit is
designed to be activated after a specified time to determine
whether it is a transient situation or an overload situation. In
conjunction with the Ipk current limit pin (if used) the cur-
rent mode feedback path would limit the current in the Sense
FET when the maximum PWM duty cycle is attained. If the
output consumes more than this maximum power, the output
voltage (Vo) decreases below its rating voltage. This reduces
the current through the opto-coupler LED, which also
reduces the opto-coupler transistor current, thus increasing
the feedback voltage (V
back input diode is blocked and the 5uA current source (I
LAY
V
tion is terminated as shown in Figure 6. The shutdown delay
time is the time required to charge Cfb from 3V to 6V with
5uA current source.
FB
) starts to charge Cfb slowly up to Vcc. In this condition,
increases until it reaches 6V, when the switching opera-
LEB
) after the Sense FET is turned on.
START
STOP
(12V), the FPS resumes its normal
FB
). If V
(8V), the protection is reset and
FSDL0365RN, FSDM0365RN
FB
exceeds 3V, the feed-
DE-
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