HYB39S256800CTL-8

Manufacturer Part NumberHYB39S256800CTL-8
ManufacturerInfineon Technologies
HYB39S256800CTL-8 datasheet
 

Specifications of HYB39S256800CTL-8

Lead Free Status / Rohs StatusNot Compliant  
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256 MBit Synchronous DRAM
High Performance:
-7.5
-8
-8A
fCK
133
125
125
tCK3
7.5
8
8
tAC3
5.4
6
6
tCK2
10
10
12
tAC2
6
6
6
Fully Synchronous to Positive Clock Edge
0 to 70 C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8
Full page burst length (optional) for
sequential wrap around
The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.17 m 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply and are available in TSOPII packages.
INFINEON Technologies
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
Multiple Burst Read with Single Write
Operation
Units
Automatic
Command
MHz
Data Mask for Read / Write control (x4, x8)
ns
Data Mask for byte control (x16)
ns
Auto Refresh (CBR) and Self Refresh
ns
Power Down and Clock Suspend Mode
ns
8192 refresh cycles / 64 ms (7,8 s)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
-8A parts for PC100 3-2-2 operation
1
and
Controlled
Precharge
8.00

HYB39S256800CTL-8 Summary of contents

  • Page 1

    ... CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages. INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Multiple Burst Read with Single Write • ...

  • Page 2

    ... RAS Row Address Strobe CAS Column Address Strobe WE Write Enable A0-A12 Address Inputs BA0, BA1 Bank Select INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Package Description P-TSOP-54-2 (400mil) 133MHz 4B x 16M x 4 SDRAM P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM P-TSOP-54-2 (400mil) ...

  • Page 3

    ... N.C. DQ6 DQ3 V V SSQ SSQ DQ7 N. LDQM N. CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/AP A10/ TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch) Pinout for x4, x8 & x16 organised 256M-DRAMs INFINEON Technologies N. DDQ N. DQ0 SSQ N. N. DDQ N. DQ1 ...

  • Page 4

    ... Counter Row Decoder Memory Array Bank 0 8196 x 2048 x 4 Bit Input Buffer DQ0 - DQ3 Block Diagram for 64M x 4 SDRAM ( addressing) INFINEON Technologies Column Addresses Row Addresses A0 - A9, A11, AP A12, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Row Decoder ...

  • Page 5

    ... Counter Row Decoder Memory Array Bank 0 8192 x 1024 x 8 Bit Input Buffer DQ0 - DQ7 Block Diagram for 32M x 8 SDRAM ( addressing) INFINEON Technologies Column Addresses Row Addresses A0 - A9, AP A12, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Row Decoder Memory ...

  • Page 6

    ... Column Address Counter Row Decoder Memory Array Bank 0 8192 x 512 x 16 Bit Input Buffer DQ0 - DQ15 Block Diagram for 16M x16 SDRAM ( addressing) INFINEON Technologies Column Addresses Row Addresses A0 - A8, AP A12, BA0, BA1 BA0, BA1 Column Address Row Address Buffer Row Decoder ...

  • Page 7

    ... DQx Input Level – Output INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode ...

  • Page 8

    ... V Supply – – DDQ V SSQ INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM ...

  • Page 9

    ... This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can’t be entered in a burst cycle. When this command assert in the burst mode cycle device is clock suspend mode. INFINEON Technologies CKE CKE DQM BA0 ...

  • Page 10

    ... Operation Mode Operation Mode M9 Mode 0 burst read / burst write 1 burst read / single write CAS Latency optional feature on this device INFINEON Technologies CAS Latency Burst Type Burst Length M2 Latency Reserved 0 Reserved Reserved HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Address Bus (Ax) BT Burst Length Mode Register (Mx) ...

  • Page 11

    ... Full page burst operation is only possible using sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do nor self terminate once the burst length has been reached. In other words, unlike burst length full page burst INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM , from the RAS timing ...

  • Page 12

    ... The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic INFINEON Technologies : Sequential Burst Addressing ...

  • Page 13

    ... CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr (“write recovery time” clocks minimum from the last data out to apply the precharge command. INFINEON Technologies ). It also provides a data mask function for writes. When DQM is DQZ ) ...

  • Page 14

    ... Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Bank Selection by Address Bits ...

  • Page 15

    ... V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Capacitance 3 Parameter Input capacitance (CLK) Input capacitance (A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM) Input / Output capacitance (DQ) INFINEON Technologies ............................................................................ – 0 4.6 V DDQ V = 3.3 V 0.3 V DDQ Symbol min – 0 ...

  • Page 16

    ... MHz for -8/-8A devices. Input signals are changed once during tck. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM o C, Vdd = 3 ...

  • Page 17

    ... CKE Setup Time CKE Hold Time Mode Register set to Active delay Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM = 3 Symbol Limit Values -7 ...

  • Page 18

    ... Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM Symbol Limit Values -7.5 -8 PC133- ...

  • Page 19

    ... Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 8. The write recovery time twr = 2 CLK cycles is a digital interlock on this device. Special devices with twr = 1 CLK for operations at less or equal 83 MHz will be available. INFINEON Technologies HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM = 2 ...

  • Page 20

    ... Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side 2) Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side INFINEON Technologies 15˚ ±5˚ 15˚ ±5˚ 0.1 54x 20.8 ...

  • Page 21

    ... CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst INFINEON Technologies HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 21 ...

  • Page 22

    ... NOP Activate "H" or "L" 2. Burst Read Operation (Burst Length = 4, CAS latency = CLK Command Read A NOP CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 INFINEON Technologies T T Bank B Col. Addr. t RCD Write B NOP with Auto Precharge NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 ...

  • Page 23

    ... DQ’s CK3 4. Read to Write Interval 4.1 Read to Write Interval (Burst Length = 4, CAS latency = CLK DQMx Command NOP Read A DQ’s "H" or "L" INFINEON Technologies NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT A0 DOUT Minimum delay between the Read and Write ...

  • Page 24

    ... Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = CLK DQM Command NOP Read A CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 "H" or "L" INFINEON Technologies DQW t DQZ 1 Clk Interval Bank A NOP Read A Write A Activate Must be Hi-Z before the Write Command DIN ...

  • Page 25

    ... Burst Write Operation ( (Burst Length = 4, CAS latency = CLK Command NOP Write A DQ’s DIN A0 The first data element and the Write are registered on the same clock edge. INFINEON Technologies NOP NOP NOP NOP don’t care DIN A1 DIN A2 DIN A3 Extra data is ignored after termination of a Burst ...

  • Page 26

    ... Write Interrupted by a Read (Burst Length = 4, CAS latency = CLK Command NOP Write A CAS latency = 2 DIN DQ’s CK2 CAS latency = 3 DIN DQ’s CK3 Input data for the Write is ignored. INFINEON Technologies Write B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN Read B NOP NOP NOP don’ ...

  • Page 27

    ... Command NOP Active DQ’s 7.2 Burst Read with Auto-Precharge (Burst Length = 4, CAS latency = CLK Read A Command NOP with AP CAS latency = 2 DQ’s CAS latency = 3 DQ’s INFINEON Technologies Write A NOP NOP NOP Auto Precharge DIN A0 DIN A1 Write A NOP NOP NOP Auto Precharge ...

  • Page 28

    ... RAS CAS RAx t AS Addr. RAx CAx DQM t RCD Hi-Z Ax0 Ax1 DQ Activate Command Bank A Write with Auto Precharge Command Bank A INFINEON Technologies T10 T11 T12 T13 Begin Auto Begin Auto Precharge Precharge Bank B Bank A RBx RAy RAy RAy RBx CBx ...

  • Page 29

    ... AC Parameters for a Read Timing CLK CK2 t CL CKE CKS t CS RAS CAS RAx t AS Addr. RAx DQM Hi-Z DQ Activate Command Bank A INFINEON Technologies RBx CAx RBx t RRD t RAS AC2 AC2 RCD Ax0 Ax1 Activate Read with Read Command Command Auto Precharge ...

  • Page 30

    ... Mode Register Set CLK CKE t CS RAS CAS Address Key Addr. Precharge Command All Banks Mode Register Set Command INFINEON Technologies T10 T11 T12 T13 RSC Any Command 30 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM CAS Latency = 2 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

  • Page 31

    ... BS AP Addr. DQM t RP Hi-Z DQ Precharge Command All Banks Inputs must be 1st Auto Refresh stable for 200 s Command INFINEON Technologies T10 T11 T12 Minimum of 8 Refresh Cycles are required 8th Auto Refresh Command 31 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM T13 T14 T15 T16 ...

  • Page 32

    ... T3 T4 CLK t CK2 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 t CSL t t CSL CSL Ax0 Ax1 Ax2 Ax3 Clock Clock Clock Suspend Suspend Suspend 1 Cycle 2 Cycles 3 Cycles ...

  • Page 33

    ... T3 T4 CLK t CK3 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 t CSL t t CSL CSL Ax0 Ax1 Ax2 Clock Clock Suspend Suspend 1 Cycle 2 Cycles 33 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM ...

  • Page 34

    ... AP RAx Addr. RAx CAx DQM Hi-Z DQ DAx0 DAx1 Activate Clock Command Suspend Bank A 1 Cycle Write Command Bank A INFINEON Technologies T10 T11 T12 T13 DAx2 DAx3 Clock Clock Suspend Suspend 2 Cycles 3 Cycles 34 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM Burst Length = 4, CAS Latency = 2 T14 ...

  • Page 35

    ... BA A8/AP RAx Addr. RAx CAx DQMx Hi-Z DQ DAx0 Activate Clock Command Suspend Bank A 1 Cycle Write Command Bank A INFINEON Technologies T10 T11 T12 T13 DAx1 DAx2 DAx3 Clock Clock Suspend Suspend 2 Cycles 3 Cycles 35 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM Burst Length = 4, CAS Latency = 3 ...

  • Page 36

    ... CAS RAx Addr. RAx DQM Hi-Z DQ Activate Active Command Standby Bank A Clock Suspend Clock Suspend Mode Entry Mode Exit INFINEON Technologies T10 T11 T12 T13 CAx Ax0 Ax1 Ax2 Read Clock Mask Clock Mask Command Start End Bank A 36 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM ...

  • Page 37

    ... CLK CKE t CKS CS RAS CAS Addr. DQM Hi-Z DQ All Banks Self Refresh must be idle Entry INFINEON Technologies T10 T11 T12 T13 t CKS t SREX Begin Self Refresh Exit Command Self Refresh Exit Self Refresh Command issued 37 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM T14 T15 ...

  • Page 38

    ... T4 CLK t CK2 CKE CS RAS CAS Addr. t (Minimum Interval) RP DQM Hi-Z DQ Precharge Auto Refresh Command Command All Banks INFINEON Technologies T10 T11 T12 T13 Auto Refresh Command 38 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM Burst Length = 4, CAS Latency = 2 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

  • Page 39

    ... CK2 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Read Read Command Command Bank A Bank A 39 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM ...

  • Page 40

    ... CLK t CK3 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 CAx CAy Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Read Read Command Command Bank A Bank A 40 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM ...

  • Page 41

    ... CK2 CKE CS RAS CAS RBw Addr. RBw CBw DQM DBw0 DBw1 DBw2 Activate Write Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 CBy CBx DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Write Write Precharge Command Command Command Bank B Bank B ...

  • Page 42

    ... CK3 CKE CS RAS CAS RBz Addr. RBz CBz DQM DBw0 Activate Write Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 CBx CBy DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 Write Write Command Command Bank B Bank B 42 HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM ...

  • Page 43

    ... RAS CAS RBx Addr. RBx CBx t RCD DQM t AC2 Hi-Z Bx0 Bx1 DQ Activate Read Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 RAx RBy RAx CAx RBy t RP Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Activate Precharge Activate ...

  • Page 44

    ... CK3 CKE High CS RAS CAS RBx Addr. RBx CBx t RCD DQM Hi-Z DQ Activate Read Command Command Bank B Bank B INFINEON Technologies T10 T11 T12 T13 RAx RAx CAx t AC3 Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Activate Read Precharge Command Command ...

  • Page 45

    ... CKE CS RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Write Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 RBx RAy RBx CBx RAy DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 Activate Write ...

  • Page 46

    ... RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A INFINEON Technologies T10 T11 T12 T13 T14 RBx RBx CBx t WR DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 Activate Write Precharge Command ...

  • Page 47

    ... CAS RAx Addr. RAx CAx DQM DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A Precharge Termination of a Write Burst. Write Data is masked. INFINEON Technologies T10 T11 T12 RAy RAy CAy t RP DAx3 Ay0 Precharge Read Precharge Command Command Command Bank A ...

  • Page 48

    ... INFINEON Technologies HYB39S256400/800/160CT(L) 256-MBit Synchronous DRAM 48 ...

  • Page 49

    ... Waveform Drawing changed from SPT03927 to SPT03927_2 20.7.2000 Waveform Drawing changed from SPT03911 to SPT03911_2 ICC6 for Low Power Versions changed from 1.5 to 1.7 mA 8.8.2000 INFINEON Technologies First Rev. Changes on pages 1, 8 & 15 Datasheet changed from Target to Preliminary Mail from Ralf Schneider, April 12. 00 ...