IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part NumberEPM3064ATC100-10N
DescriptionIC MAX 3000A CPLD 64 100-TQFP
ManufacturerAltera
SeriesMAX® 3000A
EPM3064ATC100-10N datasheet
 

Specifications of EPM3064ATC100-10N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal3 V ~ 3.6 VNumber Of Logic Elements/blocks4
Number Of Macrocells64Number Of Gates1250
Number Of I /o66Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case100-TQFP, 100-VQFP
Voltage3.0 V ~ 3.6 VMemory TypeEEPROM
Number Of Logic Elements/cells4Lead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names544-1974
EPM3064ATC100-10N
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MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
MAX 3000A device timing can be analyzed with the Altera software, with
a variety of popular industry–standard EDA simulators and timing
analyzers, or with the timing model shown in
devices have predictable internal delays that enable the designer to
determine the worst–case timing of any design. The software provides
timing simulation, point–to–point delay prediction, and detailed timing
analysis for device–wide performance evaluation.
Figure 10. MAX 3000A Timing Model
Input
Delay
t
I N
PIA
Delay
t
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin–to–pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
26
Internal Output
Enable Delay
t
IOE
Global Control
Delay
t
GLOB
Parallel
Logic Array
Expander Delay
Delay
t
PEXP
t
LAD
Register
Control Delay
t
LAC
t
I C
t
EN
Shared
Expander Delay
t
SEXP
Figure 11
Figure
10. MAX 3000A
Output
Register
Delay
Delay
t
t
SU
OD1
t
t
H
OD2
t
t
PRE
OD3
t
t
CLR
XZ
t
t
RD
Z
X1
t
t
COMB
Z X2
t
Z X3
I/O
Delay
t
I O
shows the timing relationship
Altera Corporation