MPC852TCVR100A Freescale Semiconductor, MPC852TCVR100A Datasheet - Page 14

• Manufacturer Part Number: MPC852TCVR100A
• Description: IC MPU POWERQUICC 100MHZ 256PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC852TCVR100A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 100MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC852TADS-KIT
• Maximum Clock Frequency: 100 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 4 KB
• Program Memory Type: EPROM/Flash
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Bus Signal Timing
12 Bus Signal Timing
The maximum bus speed that the MPC852T supports is 66 MHz.
standard part frequencies.
Table 9
The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays. CLKOUT assumes a 100-pF load maximum delay
14
Core
Bus
Core
Bus 2:1
Num
B1a
B1b
B1c
B1d
B1
B2
Part Frequency
provides the bus operation timing for the MPC852T at 33, 40, 50, and 66 MHz.
Bus period (CLKOUT) See
EXTCLK to CLKOUT phase skew—If
CLKOUT is an integer multiple of
EXTCLK, then the rising edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
CLKOUT frequency jitter peak-to-peak
Frequency jitter on EXTCLK
CLKOUT phase jitter peak-to-peak for
OSCLK ≥ 15 MHz
CLKOUT phase jitter peak-to-peak for
OSCLK < 15 MHz
CLKOUT pulse width low (MIN = 0.4 × B1,
MAX = 0.6 × B1)
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Characteristic
Part Frequency
Min
40
20
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
50 MHz
Table 7
1
Max
50
25
Table 9. Bus Operation Timings
12.1
Min
Min
–2
—
—
—
—
—
40
20
33 MHz
66 MHz
Max
0.50
18.2
+2
—
1
4
5
66.67
33.33
Max
10.0
Min
–2
—
—
—
—
—
40 MHz
Min
40
40
Max
0.50
15.0
Table 7
50 MHz
+2
—
Min
1
4
5
40
20
80 MHz
Min
8.0
—
–2
—
—
—
—
Max
shows the frequency ranges for
50
50
50 MHz
Max
80
40
Max
0.50
12.0
+2
—
1
4
5
Freescale Semiconductor
Min
Min
40
40
6.1
–2
—
—
—
—
—
Min
66 MHz
40
20
66 MHz
100 MHz
Max
0.50
9.1
+2
—
1
4
5
66.67
66.67
Max
Max
100
50
Unit
ns
ns
ns
ns
ns
ns
%