MPC852TCVR100A Freescale Semiconductor, MPC852TCVR100A Datasheet - Page 20

• Manufacturer Part Number: MPC852TCVR100A
• Description: IC MPU POWERQUICC 100MHZ 256PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC852TCVR100A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 100MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC852TADS-KIT
• Maximum Clock Frequency: 100 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 4 KB
• Program Memory Type: EPROM/Flash
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Bus Signal Timing
20
B32a
B32b
B32d
B33a
B34a
B34b
B35a
Num
B32c
B33
B34
B35
CLKOUT falling edge to BS valid - as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 × B1 + 6.80)
CLKOUT rising edge to BS valid - as
requested by control bit BST2 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 8.00)
CLKOUT rising edge to BS valid - as
requested by control bit BST3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
CLKOUT falling edge to BS valid- as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375 × B1 + 6.60)
CLKOUT falling edge to GPL valid - as
requested by control bit GxT4 in the
corresponding word in the UPM
(MAX = 0.00 × B1 + 6.00)
CLKOUT rising edge to GPL Valid - as
requested by control bit GxT3 in the
corresponding word in the UPM
(MAX = 0.25 × B1 + 6.80)
A(0:31), BADDR(28:30), and D(0:31) to
CS valid - as requested by control bit
CST4 in the corresponding word in the
UPM (MIN = 0.25 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to
CS valid - as requested by control bit
CST1 in the corresponding word in the
UPM (MIN = 0.50 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to
CS valid - as requested by CST2 in the
corresponding word in UPM
(MIN = 0.75 × B1 – 2.00)
A(0:31), BADDR(28:30) to CS valid - as
requested by control bit BST4 in the
corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to
BS valid - As Requested by BST1 in the
corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
Characteristic
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Table 9. Bus Operation Timings (continued)
13.30
13.20
20.70
13.20
7.60
1.50
7.60
1.50
7.60
5.60
5.60
Min
33 MHz
14.30
14.30
18.00
14.30
Max
8.00
6.00
—
—
—
—
—
11.30
10.50
16.70
10.50
6.30
1.50
6.30
1.50
6.30
4.30
4.30
Min
40 MHz
13.00
13.00
16.00
13.00
Max
8.00
6.00
—
—
—
—
—
13.00
5.00
1.50
5.00
9.40
1.50
5.00
3.00
8.00
3.00
8.00
Min
50 MHz
11.80
11.80
14.10
11.80
Max
8.00
6.00
—
—
—
—
—
Freescale Semiconductor
3.80
3.80
7.60
3.80
9.40
1.80
5.60
1.50
1.50
1.80
5.60
Min
66 MHz
10.50
10.50
12.30
10.50
Max
8.00
6.00
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns