MC68HC000RC10

Manufacturer Part NumberMC68HC000RC10
DescriptionIC MPU 32BIT 10MHZ 68-PGA
ManufacturerFreescale Semiconductor
MC68HC000RC10 datasheet
 


Specifications of MC68HC000RC10

Processor TypeM680x0 32-BitSpeed10MHz
Voltage3.3V, 5VMounting TypeSurface Mount
Package / Case68-PGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-  
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Freescale Semiconductor, Inc.
µ MOTOROLA
Microprocessors User’s Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
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©MOTOROLA INC., 1993
For More Information On This Product,
M68000
8-/16-/32-Bit
Ninth Edition
Go to: www.freescale.com
are
µ

MC68HC000RC10 Summary of contents

  • Page 1

    ... Freescale Semiconductor, Inc. µ MOTOROLA Microprocessors User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...

  • Page 2

    ... Freescale Semiconductor, Inc. Paragraph Number 1.1 MC68000..................................................................................................... 1-1 1.2 MC68008..................................................................................................... 1-2 1.3 MC68010..................................................................................................... 1-2 1.4 MC68HC000................................................................................................ 1-2 1.5 MC68HC001................................................................................................ 1-3 1.6 MC68EC000 ................................................................................................ 1-3 2.1 Programmer's Model ................................................................................... 2-1 2.1.1 User's Programmer's Model .................................................................... 2-1 2.1.2 Supervisor Programmer's Model ............................................................. 2-2 2.1.3 Status Register ........................................................................................ 2-3 2 ...

  • Page 3

    ... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 4.1 Data Transfer Operations............................................................................. 4-1 4.1.1 Read Operations ...................................................................................... 4-1 4.1.2 Write Cycle ............................................................................................... 4-3 4.1.3 Read-Modify-Write Cycle.......................................................................... 4-5 4.2 Other Bus Operations............................................................................... 4-8 5.1 Data Transfer Operations............................................................................ 5-1 5.1.1 Read Operations ..................................................................................... 5-1 5.1.2 Write Cycle .............................................................................................. 5-4 5 ...

  • Page 4

    ... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 6.2.4 Exception Stack Frames.......................................................................... 6-9 6.2.5 Exception Processing Sequence ............................................................ 6-11 6.3 Processing of Specific Exceptions ............................................................. 6-11 6.3.1 Reset ...................................................................................................... 6-11 6.3.2 Interrupts ................................................................................................ 6-12 6.3.3 Uninitialized Interrupt .............................................................................. 6-13 6.3.4 Spurious Interrupt ................................................................................... 6-13 6.3.5 Instruction Traps ..................................................................................... 6-13 6 ...

  • Page 5

    ... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 8.1 Operand Effective Address Calculation Times ........................................... 8-1 8.2 Move Instruction Execution Times .............................................................. 8-2 8.3 Standard Instruction Execution Times ........................................................ 8-3 8.4 Immediate Instruction Execution Times ...................................................... 8-4 8.5 Single Operand Instruction Execution Times .............................................. 8-5 8.6 Shift/Rotate Instruction Execution Times ...

  • Page 6

    ... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Electrical and Thermal Characteristics 10.9 MC68008 AC Electrical Specifications—Clock Timing ............................. 10-9 10.10 AC Electrical Specifications—Read and Write Cycles ............................ 10-10 10.11 AC Electrical Specifications—MC68000 To M6800 Peripheral............... 10-15 10.12 AC Electrical Specifications—Bus Arbitration ......................................... 10-17 10.13 MC68EC000 DC Electrical Spec ifications ...

  • Page 7

    ... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure Number 2-1 User Programmer's Model ................................................................................... 2-2 2-2 Supervisor Programmer's Model Supplement ..................................................... 2-2 2-3 Supervisor Programmer's Model Supplement (MC68010) .................................. 2-3 2-4 Status Register .................................................................................................... 2-3 2-5 Word Organization In Memory ............................................................................. 2-6 2-6 Data Organization In Memory .............................................................................. 2-7 2-7 Memory Data Organization (MC68008) ............................................................... 2-3 3-1 Input and Output Signals (MC68000, MC68HC000, MC68010) ...

  • Page 8

    ... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number 5-15 3-Wire Bus Arbitration Timing Diagram (NA to 48-Pin MC68008 and MC68EC000 ........................................................ 5-13 5-16 2-Wire Bus Arbitration Timing Diagram.............................................................. 5-14 5-17 External Asynchronous Signal Synchronization ................................................. 5-16 5-18 Bus Arbitration Unit State Diagrams................................................................... 5-17 5-19 3-Wire Bus Arbitration Timing Diagram— ...

  • Page 9

    ... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Concluded) Figure Number 10-7 Bus Arbitration Timing...................................................................................... 10-18 10-8 Bus Arbitration Timing...................................................................................... 10-19 10-9 Bus Arbitration Timing—Idle Bus Case ............................................................ 10-20 10-10 Bus Arbitration Timing—Active Bus Case........................................................ 10-21 10-11 Bus Arbitration Timing—Multiple Bus Request ................................................ 10-22 10-12 MC68EC000 Read Cycle Timing Diagram ...

  • Page 10

    ... Freescale Semiconductor, Inc. Table Number 2-1 Data Addressing Modes ....................................................................................... 2-4 2-2 Instruction Set Summary .................................................................................... 2-11 3-1 Data Strobe Control of Data Bus.......................................................................... 3-5 3-2 Data Strobe Control of Data Bus (MC68008)....................................................... 3-5 3-3 Function Code Output .......................................................................................... 3-9 3-4 Signal Summary ................................................................................................. 3-10 5-1 DTACK, BERR, and HALT Assertion Results ..................................................... 5-31 6-1 Reference Classification ...

  • Page 11

    ... Freescale Semiconductor, Inc. LIST OF TABLES (Concluded) Table Number 8-5 Standard Instruction Execution Times ................................................................. 8-4 8-6 Immediate Instruction Execution Times ............................................................... 8-5 8-7 Single Operand Instruction Execution Times ....................................................... 8-6 8-8 Shift/Rotate Instruction Execution Times ............................................................. 8-6 8-9 Bit Manipulation Instruction Execution Times ...................................................... 8-7 8-10 Conditional Instruction Execution Times ...

  • Page 12

    ... Freescale Semiconductor, Inc. SECTION 1 OVERVIEW This manual includes hardware details and programming information for the MC68000, the MC68HC000, the MC68HC001, the MC68008, the MC68010, and the MC68EC000. For ease of reading, the name M68000 MPUs will be used when referring to all processors. Refer to M68000PM/AD, M68000 Programmer's Reference Manual , for detailed information on the MC68000 instruction set ...

  • Page 13

    ... Freescale Semiconductor, Inc. 1.1 MC68000 The MC68000 is the first implementation of the M68000 16/-32 bit microprocessor architecture. The MC68000 has a 16-bit data bus and 24-bit address bus while the full architecture provides for 32-bit address and data buses completely code-compatible with the MC68008 8-bit data bus implementation of the M68000 and is upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture ...

  • Page 14

    ... Freescale Semiconductor, Inc. 1.4 MC68HC000 The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates an order of magnitude less power than the HMOS MC68000. The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The MC68HC000 has a 16-bit data bus implementation of the MC68000 and is upward code-compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture ...

  • Page 15

    ... Freescale Semiconductor, Inc. SECTION 2 INTRODUCTION The section provide a brief introduction to the M68000 microprocessors (MPUs). Detailed information on the programming model, data types, addressing modes, data organization and instruction set can be found in M68000PM/AD, M68000 Programmer's Reference Manual . All the processors are identical from the programmer's viewpoint, ...

  • Page 16

    ... Freescale Semiconductor, Inc Figure 2-1. User Programmer's Model (MC68000/MC68HC000/MC68008/MC68010) 2.1.2 Supervisor Programmer's Model The supervisor programmer's model consists of supplementary registers used in the supervisor mode. The M68000 MPUs contain identical supervisor mode register resources, which are shown in Figure 2-2, including the status register (high-order byte) and the supervisor stack pointer (SSP/A7') ...

  • Page 17

    ... Freescale Semiconductor, Inc. tables. The SFC and DFC registers allow the supervisor to access user data space or emulate CPU space cycles Figure 2-3. Supervisor Programmer's Model Supplement 2.1.3 Status Register The status register (SR),contains the interrupt mask (eight levels available) and the following condition codes: overflow (V), zero (Z), negative (N), carry (C), and extend (X) ...

  • Page 18

    ... Freescale Semiconductor, Inc. In addition, operations on other data types, such as memory addresses, status word data, etc., are provided in the instruction set. The 14 flexible addressing modes, shown in Table 2-1, include six basic types: 1. Register Direct 2. Register Indirect 3. Absolute 4. Immediate 5. Program Counter Relative 6. Implied The register indirect addressing modes provide postincrementing, predecrementing, offsetting, and indexing capabilities ...

  • Page 19

    ... Freescale Semiconductor, Inc. Table 2-1. Data Addressing Modes Mode Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with Offset Relative with Index and Offset Register Indirect Addressing Register Indirect ...

  • Page 20

    ... Freescale Semiconductor, Inc. When a data register is used as either a source or a destination operand, only the appropriate low-order portion is changed; the remaining high-order portion is neither used nor changed. 2.3.2 Address Registers Each address register (and the stack pointer bits wide and holds a full, 32-bit address ...

  • Page 21

    ... Freescale Semiconductor, Inc BYTE 0 MSB BYTE MSB EVEN BYTE MSB LONG WORD 0 LONG WORD 1 LONG WORD MSB ADDRESS 0 ADDRESS 1 ADDRESS 2 MSB = MOST SIGNIFICANT BIT LSB = LEAST SIGNIFICANT BIT MSD BCD 0 BCD 4 MSD = MOST SIGNIFICANT DIGIT LSD = LEAST SIGNIFICANT DIGIT Figure 2-6. Data Organization in Memory MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’ ...

  • Page 22

    ... Freescale Semiconductor, Inc INTEGER DATA 1 BYTE = 8 BITS 7 6 BYTE 0 (MS BYTE) BYTE 1 (LS BYTE) BYTE 0 (MS BYTE) BYTE 1 (LS BYTE) 1 LONG WORD = 2 WORDS = 4 BYTES = 32 BITS BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 0 BYTE 1 BYTE 2 BYTE 3 Figure 2-7. Memory Data Organization of the MC68008 2.5 ...

  • Page 23

    ... Freescale Semiconductor, Inc. Notation for operands: PC — Program counter SR — Status register V — Overflow condition code Immediate Data — Immediate data from the instruction Source — Source contents Destination — Destination contents Vector — Location of exception vector +inf — Positive infinity – ...

  • Page 24

    ... Freescale Semiconductor, Inc. shifted by, rotated by — The source operand is shifted or rotated by the number of Notation for single-operand operations: ~<operand> — The operand is logically complemented <operand>sign-extended — The operand is sign-extended, all bits of the upper <operand>tested — The operand is compared to zero and the condition Notation for other operations: TRAP — ...

  • Page 25

    ... Freescale Semiconductor, Inc. Table 2-2. Instruction Set Summary (Sheet Opcode ABCD Source 10 + Destination ADD Source + Destination ADDA Source + Destination ADDI Immediate Data + Destination ADDQ Immediate Data + Destination ADDX Source + Destination + X AND Source Destination ANDI Immediate Data Destination ANDI to CCR Source CCR ...

  • Page 26

    ... Freescale Semiconductor, Inc. Table 2-2. Instruction Set Summary (Sheet Opcode DIVS Destination/Source DIVU Destination/Source EOR Source Destination EORI Immediate Data Destination EORI to CCR Source CCR CCR EORI supervisor state then Source SR SR else TRAP EXG Rx Ry EXT Destination Sign-Extended ILLEGAL SSP – 2 SSP ...

  • Page 27

    ... Freescale Semiconductor, Inc. Table 2-2. Instruction Set Summary (Sheet Opcode MOVE USP If supervisor state then USP else TRAP MOVEC If supervisor state then else TRAP MOVEM Registers Destination Source Registers MOVEP Source Destination MOVEQ Immediate Data Destination MOVES If supervisor state then Rn Destination [DFC] or Source [SFC] ...

  • Page 28

    ... Freescale Semiconductor, Inc. Table 2-2. Instruction Set Summary (Sheet Opcode RTE If supervisor state then (SP) SR SP; restore state and deallocate stack according to (SP) else TRAP RTR (SP) CCR (SP) PC RTS (SP) PC SBCD Destination 10 – Source 10 – X Scc If condition true then 1s Destination else 0s Destination ...

  • Page 29

    ... Freescale Semiconductor, Inc. SECTION 3 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals. The input and output signals can be functionally organized into the groups shown in Figure 3-1 (for the MC68000, the MC68HC000 and the MC68010), Figure 3-2 ( for the MC68HC001), Figure 3-3 (for the MC68EC000), Figure 3-4 (for the MC68008, 48-pin version), and Figure 3-5 (for the MC68008, 52-pin version) ...

  • Page 30

    ... Freescale Semiconductor, Inc. PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-2. Input and Output Signals PROCESSOR STATUS SYSTEM CONTROL Figure 3-3. Input and Output Signals 3-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product (2) ADDRESS GND(2) BUS ...

  • Page 31

    ... Freescale Semiconductor, Inc. PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-4. Input and Output Signals (MC68008, 48-Pin Version) PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-5. Input and Output Signals (MC68008, 52-Pin Version) 3.1 ADDRESS BUS (A23–A1) This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data. ...

  • Page 32

    ... Freescale Semiconductor, Inc. Address Bus (A23–A0) This 24-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data. This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3 provide the level number of the interrupt being acknowledged, and address lines A23– ...

  • Page 33

    ... Freescale Semiconductor, Inc. Table 3-1. Data Strobe Control of Data Bus UDS LDS High High Low Low High Low Low High Low Low High Low Low High *These conditions are a result of current implementation and may not appear on future devices. DS Data Strobe ( ) (MC68008) This three-state signal and R/W control the flow of data on the data bus of the MC68008 ...

  • Page 34

    ... Freescale Semiconductor, Inc. BR Bus Request ( ). This input can be wire-ORed with bus request signals from all other devices that could be bus masters. This signal indicates to the processor that some other device needs to become the bus master. Bus requests can be issued at any time during a cycle or between cycles ...

  • Page 35

    ... Freescale Semiconductor, Inc. 3.6 SYSTEM CONTROL The system control inputs are used to reset the processor, to halt the processor, and to signal a bus error to the processor. The outputs reset the external devices in the system and signal a processor error halt to those devices. The three system control signals are described in the following paragraphs ...

  • Page 36

    ... Freescale Semiconductor, Inc. 3.7 M6800 PERIPHERAL CONTROL These control signals are used to interface the asynchronous M68000 processors with the synchronous M6800 peripheral devices. These signals are described in the following paragraphs. Enable (E) This signal is the standard enable signal common to all M6800 Family peripheral devices ...

  • Page 37

    ... Freescale Semiconductor, Inc. Table 3-3. Function Code Outputs Function Code Output FC2 Low Low Low Low High High High High 3.9 CLOCK (CLK) The clock input is a TTL-compatible signal that is internally buffered for development of the internal clocks needed by the processor. This clock signal is a constant frequency square wave that requires no stretching or shaping ...

  • Page 38

    ... Freescale Semiconductor, Inc. 3.11 SIGNAL SUMMARY Table 3-4 summarizes the signals discussed in the preceding paragraphs. Signal Name Address Bus Data Bus Address Strobe Read/Write Data Strobe Upper and Lower Data Strobes Data Transfer Acknowledge Bus Request Bus Grant Bus Grant Acknowledge ...

  • Page 39

    ... Freescale Semiconductor, Inc. SECTION 4 8-BIT BUS OPERATION The following paragraphs describe control signal and bus operation for 8-bit operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. The 8-bit bus operations devices are the MC68008, MC68HC001 in 8-bit mode, and MC68EC000 in 8-bit mode ...

  • Page 40

    ... Freescale Semiconductor, Inc. BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 3) PLACE ADDRESS ON A23-A0 4) ASSERT ADDRESS STROBE (AS) 5) ASSERT LOWER DATA STROBE (LDS) (DS ON MC68008) ACQUIRE THE DATA 1) LATCH DATA 2) NEGATE LDS (DS FOR MC68008) 3) NEGATE AS START NEXT CYCLE Figure 4-1 ...

  • Page 41

    ... Freescale Semiconductor, Inc. A bus cycle consists of eight states. The various signals are asserted during specific states of a read cycle, as follows: STATE 0 The read cycle starts in state 0 (S0). The processor places valid function codes on FC0–FC2 and drives R/W high to identify a read cycle. ...

  • Page 42

    ... Freescale Semiconductor, Inc. BUS MASTER ADDRESS THE DEVICE 1) PLACE FUNCTION CODE ON FC2–FC0 2) PLACE ADDRESS ON A23–A0 3) ASSERT ADDRESS STROBE (AS) 4) SET R/W TO WRITE 5) PLACE DATA ON D0–D7 6) ASSERT LOWER DATA STROBE (LDS TERMINATE OUTPUT TRANSFER 1) NEGATE LDS NEGATE AS 3) REMOVE DATA FROM D7-D0 ...

  • Page 43

    ... Freescale Semiconductor, Inc. The descriptions of the eight states of a write cycle are as follows: STATE 0 The write cycle starts in S0. The processor places valid function codes on FC2–FC0 and drives R/W high (if a preceding write cycle has left R/W low). STATE 1 Entering S1, the processor drives a valid address on the address bus. ...

  • Page 44

    ... Freescale Semiconductor, Inc. BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 3) PLACE ADDRESS ON A23–A0 4) ASSERT ADDRESS STROBE (AS) 5) ASSERT LOWER DATA STROBE (LDS) (DS ON MC68008) ACQUIRE THE DATA 1) LATCH DATA 1) NEGATE LDS START DATA MODIFICATION ...

  • Page 45

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A23– LDS R/W DTACK D7–D0 Figure 4-6. Read-Modify-Write Cycle Timing Diagram The descriptions of the read-modify-write cycle states are as follows: STATE 0 The read cycle starts in S0. The processor places valid function codes on FC2–FC0 and drives R/W high to identify a read cycle. ...

  • Page 46

    ... Freescale Semiconductor, Inc. STATE 12 The write portion of the cycle starts in S12. The valid function codes on FC2–FC0, the address bus lines, AS, and R/W remain unaltered. STATE 13 During S13, no bus signals are altered. STATE 14 On the rising edge of S14, the processor drives R/W low. ...

  • Page 47

    ... Freescale Semiconductor, Inc. SECTION 5 16-BIT BUS OPERATION The following paragraphs describe control signal and bus operation for 16-bit bus operations during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. The 16-bit bus operation devices are the MC68000, MC68HC000, MC68010, and the MC68HC001 and MC68EC000 in 16-bit mode ...

  • Page 48

    ... Freescale Semiconductor, Inc. BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 3) PLACE ADDRESS ON A23–A1 4) ASSERT ADDRESS STROBE (AS) 5) ASSERT UPPER DATA STROBE (UDS) AND LOWER DATA STROBE (LDS) ACQUIRE THE DATA 1) LATCH DATA 2) NEGATE UDS AND LDS ...

  • Page 49

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D8 D7–D0 READ Figure 5-3. Read and Write-Cycle Timing Diagram CLK FC2–FC0 A23– UDS LDS R/W DTACK D15–D8 D7–D0 READ *Internal Signal Only Figure 5-4. Word and Byte Read-Cycle Timing Diagram ...

  • Page 50

    ... Freescale Semiconductor, Inc. A bus cycle consists of eight states. The various signals are asserted during specific states of a read cycle, as follows: STATE 0 The read cycle starts in state 0 (S0). The processor places valid function codes on FC0–FC2 and drives R/W high to identify a read cycle. ...

  • Page 51

    ... Freescale Semiconductor, Inc. The word and byte write-cycle timing diagram and flowcharts in Figures 5-5, 5-6, and 5-7 applies directly to the MC68000, the MC68HC000, the MC68HC001 (in 16-bit mode), the MC68EC000 (in 16-bit mode), and the MC68010. BUS MASTER ADDRESS THE DEVICE 1) PLACE FUNCTION CODE ON FC2–FC0 2) PLACE ADDRESS ON A23– ...

  • Page 52

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A23– UDS LDS R/W DTACK D15–D8 D7–D0 *INTERNAL SIGNAL ONLY WORD WRITE Figure 5-7. Word and Byte Write-Cycle Timing Diagram The descriptions of the eight states of a write cycle are as follows: STATE 0 The write cycle starts in S0. The processor places valid function codes on FC2– ...

  • Page 53

    ... Freescale Semiconductor, Inc. STATE 7 On the falling edge of the clock entering S7, the processor negates AS, UDS, or LDS. As the clock rises at the end of S7, the processor places the address and data buses in the high-impedance state, and drives R/W high. The device negates DTACK or BERR at this time. ...

  • Page 54

    ... Freescale Semiconductor, Inc CLK A23–A1 AS UDS OR LDS R/W DTACK D15–D8 FC2–FC0 Figure 5-9. Read-Modify-Write Cycle Timing Diagram The descriptions of the read-modify-write cycle states are as follows: STATE 0 The read cycle starts in S0. The processor places valid function codes on FC2–FC0 and drives R/W high to identify a read cycle. ...

  • Page 55

    ... Freescale Semiconductor, Inc. STATE 12 The write portion of the cycle starts in S12. The valid function codes on FC2–FC0, the address bus lines, AS, and R/W remain unaltered. STATE 13 During S13, no bus signals are altered. STATE 14 On the rising edge of S14, the processor drives R/W low. ...

  • Page 56

    ... Freescale Semiconductor, Inc. The interrupt acknowledge cycle places the level of the interrupt being acknowledged on address bits A3–A1 and drives all other address lines high. The interrupt acknowledge cycle reads a vector number when the interrupting device places a vector number on the data bus and asserts DTACK to acknowledge the cycle. ...

  • Page 57

    ... Freescale Semiconductor, Inc. The breakpoint acknowledge cycle is performed by the MC68010 to provide an indication to hardware that a software breakpoint is being executed when the processor executes a breakpoint (BKPT) instruction. The processor neither accepts nor sends data during this cycle, which is otherwise similar to a read cycle. The cycle is terminated by either DTACK, BERR M6800 peripheral cycle when asserted, and the processor continues illegal instruction exception processing ...

  • Page 58

    ... Freescale Semiconductor, Inc. PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-13. 3-Wire Bus Arbitration Cycle Flowchart (Not Applicable to 48-Pin MC68008 or MC68EC000) 5-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

  • Page 59

    ... Freescale Semiconductor, Inc. PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE RELEASE OF BUS MASTERSHIP 1) NEGATE BUS GRANT (BG) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-14. 2-Wire Bus Arbitration Cycle Flowchart CLK FC2–FC0 A23–A1 AS LDS/ UDS R/W DTACK D15– BGACK PROCESSOR DMA DEVICE Figure 5-15 ...

  • Page 60

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A19– R/W DTACK D7– PROCESSOR DMA DEVICE Figure 5-16. 2-Wire Bus Arbitration Timing Diagram The timing diagram in Figure 5-15 shows that the bus request is negated at the time that an acknowledge is asserted. This type of operation applies to a system consisting of a processor and one other device capable of becoming bus master ...

  • Page 61

    ... Freescale Semiconductor, Inc. bus request signal. When no acknowledge is received before the bus request signal is negated, the processor continues the use of the bus. 5.2.2 Receiving The Bus Grant The processor asserts BG as soon as possible. Normally, this process immediately follows internal synchronization, except when the processor has made an internal decision to execute the next bus cycle but has not yet asserted AS for that cycle ...

  • Page 62

    ... Freescale Semiconductor, Inc. INTERNAL SIGNAL VALID EXTERNAL SIGNAL SAMPLED BR (EXTERNAL) BR (iNTERNAL) Figure 5-17. External Asynchronous Signal Synchronization Bus arbitration control is implemented with a finite-state machine. State diagram (a) in Figure 5-18 applies to all processors using 3-wire bus arbitration and state diagram (b) applies to processors using 2-wire bus arbitration, in which BGACK is permanently negated internally or externally ...

  • Page 63

    ... Freescale Semiconductor, Inc STATE STATE Bus Request Internal A = Bus Grant Acknowledge Internal G = Bus Grant T = Three-state Control to Bus Control Logic X = Don't Care Figure 5-18. Bus Arbitration Unit State Diagrams Figures 5-19, 5-20, and 5-21 applies to all processors using 3-wire bus arbitration. Figures 5-22, 5-23, and 5-24 applies to all processors using 2-wire bus arbitration ...

  • Page 64

    ... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active 5-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, ...

  • Page 65

    ... Freescale Semiconductor, Inc. BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-20. 3-Wire Bus Arbitration Timing Diagram—Bus Inactive ...

  • Page 66

    ... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case 5-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, ...

  • Page 67

    ... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-22. 2-Wire Bus Arbitration Timing Diagram—Processor Active MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, ...

  • Page 68

    ... Freescale Semiconductor, Inc. BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-23. 2-Wire Bus Arbitration Timing Diagram—Bus Inactive ...

  • Page 69

    ... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-24. 2-Wire Bus Arbitration Timing Diagram—Special Case 5.4. BUS ERROR AND HALT OPERATION In a bus architecture that requires a handshake from an external device, such as the asynchronous bus used in the M68000 Family, the handshake may not always occur ...

  • Page 70

    ... Freescale Semiconductor, Inc. The MC68010 also differs from the other microprocessors described in this manual regarding bus errors. The MC68010 can detect a late bus error signal asserted within one clock cycle after the assertion of data transfer acknowledge. When receiving a bus error signal, the processor can either initiate a bus error exception sequence or try running the cycle again ...

  • Page 71

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A23–A1 AS UDS/LDS R/W DTACK D15–D0 BERR HALT READ CYCLE Figure 5-26. Delayed Bus Error Timing Diagram (MC68010) After the aborted bus cycle is terminated and BERR is negated, the processor enters exception processing for the bus error exception. During the exception processing sequence, the following information is placed on the supervisor stack: 1 ...

  • Page 72

    ... Freescale Semiconductor, Inc. In the MC68010 read-modify-write operation terminates in a bus error, the processor reruns the entire read-modify-write operation when the RTE instruction at the end of the bus error handler returns control to the instruction in error. The processor reruns the entire operation whether the error occurred during the read or write portion ...

  • Page 73

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D0–D15 BERR HALT READ Figure 5-28. Delayed Retry Bus Cycle Timing Diagram The processor terminates the bus cycle, then puts the address and data lines in the high- impedance state. The processor remains in this state until HALT is negated. Then the processor retries the preceding cycle using the same function codes, address, and data (for a write operation) ...

  • Page 74

    ... Freescale Semiconductor, Inc CLK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D0–D15 BERR HALT READ Figure 5-29. Halt Operation Timing Diagram While the processor is halted, the address bus and the data bus signals are placed in the high-impedance state. Bus arbitration is performed as usual. Should a bus error occur while HALT is asserted, the processor performs the retry operation previously described ...

  • Page 75

    ... Freescale Semiconductor, Inc. A double bus fault occurs during a reset operation when a bus error occurs while the processor is reading the vector table (before the first instruction is executed). The reset operation is described in the following paragraph. 5.5 RESET OPERATION RESET is asserted externally for the initial processor reset. Subsequently, the signal can be asserted either externally or internally (executing a RESET instruction) ...

  • Page 76

    ... Freescale Semiconductor, Inc. executing a reset instruction is ignored. Since the processor asserts the RESET signal for 124 clock cycles during execution of a reset instruction, an external reset should assert RESET for at least 132 clock periods. 5.6 THE RELATIONSHIP OF To properly control termination of a bus cycle for a retry or a bus error condition, DTACK, BERR, and HALT should be asserted and negated on the rising edge of the processor clock ...

  • Page 77

    ... Freescale Semiconductor, Inc. DTACK Table 5-1. Asserted on Case Control Rising Edge No. Signal of State N N+2 1 DTACK A S Normal cycle terminate and continue. BERR HALT Normal cycle terminate and halt. DTACK BERR NA NA Continue when HALT negated. HALT A DTACK X X Terminate and take bus error trap. ...

  • Page 78

    ... Freescale Semiconductor, Inc. 4. For an MC68010, return DTACK before data verification. If data is invalid, assert BERR on the next clock cycle (case 4). Table 5-6. Conditions of Termination in Table 4-4 Control Signal Bus Error BERR HALT Rerun BERR HALT Rerun BERR HALT Normal BERR HALT Normal ...

  • Page 79

    ... Freescale Semiconductor, Inc. ADDR AS R/W UDS/LDS DATA DTACK Figure 5-32. Fully Asynchronous Write Cycle In the asynchronous mode, the accessed device operates independently of the frequency and phase of the system clock. For example, the MC68681 dual universal asynchronous receiver/transmitter (DUART) does not require any clock-related information from the bus master during a bus transfer ...

  • Page 80

    ... Freescale Semiconductor, Inc. ADDR AS 17 R/W UDS/LDS DATA DTACK Figure 5-33. Pseudo-Asynchronous Read Cycle During a write cycle, after the processor asserts AS but before driving the data bus, the processor drives R/W low. Parameter #55 specifies the minimum time between the transition of R/W and the driving of the data bus, which is effectively the maximum turnoff time for any device driving the data bus ...

  • Page 81

    ... Freescale Semiconductor, Inc. ADDR AS R/W UDS/LDS DATA DTACK Figure 5-34. Pseudo-Asynchronous Write Cycle In the MC68010, the BERR signal can be delayed after the assertion of DTACK. Specification #48 is the maximum time between assertion of DTACK and assertion of BERR. If this maximum delay is exceeded, operation of the processor may be erratic. ...

  • Page 82

    ... Freescale Semiconductor, Inc. is the maximum hold time for a low on R/W beyond the initiation of the read cycle. STATE 1 Entering S1, a low period of the clock, the address of the accessed device is driven externally with an assertion delay defined by parameter #6. STATE 2 On the rising edge of S2, a high period of the clock asserted. During a read cycle, UDS, LDS, and/ also asserted at this time ...

  • Page 83

    ... Freescale Semiconductor, Inc. On the rising edge of the clock, at the end of S7 (which may be the start of S0 for the next bus cycle), the processor places the address bus in the high-impedance state. During a write cycle, the processor also places the data bus in the high-impedance state and drives R/W high. External logic circuitry should respond to the negation of the AS and UDS, LDS, and/ negating DTACK and/or BERR ...

  • Page 84

    ... Freescale Semiconductor, Inc CLOCK 6 ADDR AS UDS/LDS 18 R/W DTACK DATA Figure 5-36. Synchronous Write Cycle A key consideration when designing in a synchronous environment is the timing for the assertion of DTACK and BERR by an external device. To properly use external inputs, the processor must synchronize these signals to the internal clock. The processor must ...

  • Page 85

    ... Freescale Semiconductor, Inc. Parameter #47 of Section 10 Electrical Characteristics is the asynchronous input setup time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling edge of the system clock. However, signals that do not meet parameter #47 are not guaranteed to be recognized. In addition, if DTACK is recognized on a falling edge, valid data is latched into the processor (during a read cycle) on the next falling edge, provided the data meets the setup time required (parameter #27) ...

  • Page 86

    ... Freescale Semiconductor, Inc. SECTION 6 EXCEPTION PROCESSING This section describes operations of the processor outside the normal processing associated with the execution of instructions. The functions of the bits in the supervisor portion of the status register are described: the supervisor/user bit, the trace enable bit, and the interrupt priority mask. Finally, the sequence of memory references and actions taken by the processor for exception conditions are described in detail ...

  • Page 87

    ... Freescale Semiconductor, Inc. The privilege mode is a mechanism for providing security in a computer system. Programs should access only their own code and data areas and should be restricted from accessing information that they do not need and must not modify. The operating system executes in the supervisor mode, allowing it to access all resources required to perform the overhead tasks for the user mode programs ...

  • Page 88

    ... Freescale Semiconductor, Inc. supervisor mode. Therefore, when instruction execution resumes at the address specified to process the exception, the processor is in the supervisor privilege mode. The transition from supervisor to user mode can be accomplished by any of four instructions: return from exception (RTE) (MC68010 only), move to status register (MOVE to SR), AND immediate to status register (ANDI to SR), and exclusive OR immediate to status register (EORI to SR) ...

  • Page 89

    ... Freescale Semiconductor, Inc. 6.2 EXCEPTION PROCESSING The processing of an exception occurs in four steps, with variations for different exception causes: 1. Make a temporary copy of the status register and set the status register for exception processing. 2. Obtain the exception vector. 3. Save the current processor context. ...

  • Page 90

    ... Freescale Semiconductor, Inc. D15 IGNORED Where the MSB of the vector number v0 is the LSB of the vector number Figure 6-2. Peripheral Vector Number Format A31 ALL ZEROES Figure 6-3. Address Translated from 8-Bit Vector Number (MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008) 31 CONTENTS OF VECTOR BASE REGISTER ...

  • Page 91

    ... Freescale Semiconductor, Inc. requests from peripheral devices for processor action; the bus error and reset inputs are used for access control and processor restart. The internal exceptions are generated by instructions, address errors, or tracing. The trap (TRAP), trap on overflow (TRAPV), check register against bounds (CHK), and divide (DIV) instructions can generate exceptions as part of their instruction execution ...

  • Page 92

    ... Freescale Semiconductor, Inc. Table 6-2. Exception Vector Assignment Vectors Numbers Hex Decimal 16–23 1 10– 20–2F 32–47 48–63 1 30–3F 40–FF 64–255 NOTES: 1. Vector numbers 12, 13, 16–23, and 48–63 are reserved for future enhancements by Motorola. No user peripheral devices should be assigned these numbers. ...

  • Page 93

    ... Freescale Semiconductor, Inc. 6.2.3 Multiple Exceptions These paragraphs describe the processing that occurs when multiple exceptions arise simultaneously. Exceptions can be grouped by their occurrence and priority. The group 0 exceptions are reset, bus error, and address error. These exceptions cause the instruction currently being executed to abort and the exception processing to commence within two clock cycles ...

  • Page 94

    ... Freescale Semiconductor, Inc. Table 6-3. Exception Grouping and Priority Group Exception 0 Reset Address Error Bus Error 1 Trace Interrupt Illegal Privilege 2 TRAP, TRAPV, CHK Zero Divide 6.2.4 Exception Stack Frames Exception processing saves the most volatile portion of the current processor context on the top of the supervisor stack. This context is organized in a format called the exception stack frame ...

  • Page 95

    ... Freescale Semiconductor, Inc SSP Figure 6-5. Group 1 and 2 Exception Stack Frame (MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 FORMAT Figure 6-6. MC68010 Stack Frame 6-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, EVEN BYTE ODD BYTE 0 7 STATUS REGISTER ...

  • Page 96

    ... Freescale Semiconductor, Inc. Table 6-4. MC68010 Format Codes Format Code All Others 6.2.5 Exception Processing Sequence In the first step of exception processing, an internal copy is made of the status register. After the copy is made, the S bit of the status register is set, putting the processor into the supervisor mode ...

  • Page 97

    ... Freescale Semiconductor, Inc. interrupt priority mask is set at level 7. In the MC68010, the VBR is forced to zero. The vector number is internally generated to reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions can be made about the validity of register contents, in particular the SSP, neither the program counter nor the status register is saved ...

  • Page 98

    ... Freescale Semiconductor, Inc. register on the supervisor stack. The offset value in the format/offset word on the MC68010 is the vector number multiplied by four. The format is all zeros. The saved value of the program counter is the address of the instruction that would have been executed had the interrupt not been taken. The appropriate interrupt vector is fetched and loaded into the program counter, and normal instruction execution commences in the interrupt handling routine ...

  • Page 99

    ... Freescale Semiconductor, Inc. A signed divide (DIVS) or unsigned divide (DIVU) instruction forces an exception if a division operation is attempted with a divisor of zero. 6.3.6 Illegal and Unimplemented Instructions Illegal instruction is the term used to refer to any of the word bit patterns that do not match the bit pattern of the first word of a legal M68000 instruction. If such an instruction is fetched, an illegal instruction exception occurs ...

  • Page 100

    ... Freescale Semiconductor, Inc. 6.3.7 Privilege Violations To provide system security, various instructions are privileged. An attempt to execute one of the privileged instructions while in the user mode causes an exception. The privileged instructions are as follows: AND Immediate to SR EOR Immediate to SR MOVE to SR (68010 only) MOVE from SR (68010 only) ...

  • Page 101

    ... Freescale Semiconductor, Inc. After the execution of the instruction is complete and before the start of the next instruction, exception processing for a trace begins. A copy is made of the status register. The transition to supervisor mode is made, and the T bit of the status register is turned off, disabling further tracing. The vector number is generated to reference the trace exception vector, and the current program counter and the copy of the status register are saved on the supervisor stack ...

  • Page 102

    ... Freescale Semiconductor, Inc. protect memory contents from erroneous accesses. Only an external reset operation can restart a halted processor LOWER ADDRESS ACCESS ADDRESS PROGRAM COUNTER R/W (Read/Write): Write=0, Read=1. I/N (Instruction/Not): Instruction=0, Not=1 Figure 6-7. Supervisor Stack Order for Bus or Address Error Exception 6 ...

  • Page 103

    ... Freescale Semiconductor, Inc 1000 VERSION NUMBER NOTE: The stack pointer is decremented by 29 words, although only 26 words of information are actually written to memory. The three additional words are reserved for future use by Motorola. . Figure 6-8. Exception Stack Order (Bus and Address Error) The value of the saved program counter does not necessarily point to the instruction that was executing when the bus error occurred, but may be advanced by as many as five words ...

  • Page 104

    ... Freescale Semiconductor, Inc. shown in Figure 6-9. If the bus cycle is a read, the data at the fault address should be written to the images of the data input buffer, instruction input buffer, or both according to the data fetch (DF) and instruction fetch (IF) bits. the status register image must be properly set to reflect the read data if the fault occurred during the read portion of the cycle and the write operation (i ...

  • Page 105

    ... Freescale Semiconductor, Inc. 6.4 RETURN FROM EXCEPTION (MC68010) In addition to returning from any exception handler routine on the MC68010, the RTE instruction resumes the execution of a suspended instruction by returning to the normal processing state after restoring all of the temporary register and control information stored during a bus error ...

  • Page 106

    ... Freescale Semiconductor, Inc. SECTION 7 8-BIT INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock (CLK) periods for the MC68008 and MC68HC001/MC68EC000 in 8-bit mode. In this data assumed that both memory read and write cycles consist of four clock periods. A longer memory cycle causes the generation of wait states that must be added to the total instruction times ...

  • Page 107

    ... Freescale Semiconductor, Inc. Table 7-1. Effective Address Calculation Times Addressing Mode Dn Data Register Direct An Address Register Direct (An) Address Register Indirect (An)+ Address Register Indirect with Postincrement –(An) Address Register Indirect with Predecrement ( An) Address Register Indirect with Displacement ( An, Xn)* Address Register Indirect with Index (xxx) ...

  • Page 108

    ... Freescale Semiconductor, Inc. Table 7-3. Move Word Instruction Execution Times Source 8(2/0) 8(2/0) 16(2/2) An 8(2/0) 8(2/0) 16(2/2) (An) 16(4/0) 16(4/0) 24(4/2) (An)+ 16(4/0) 16(4/0) 24(4/2) –(An) 18(4/0) 18(4/0) 26(4/ An) 24(6/0) 24(6/0) 32(6/ An, Xn)* 26(6/0) 26(6/0) 34(6/2) (xxx).W 24(6/0) 24(6/0) 32(6/2) (xxx).L 32(8/0) 32(8/0) ...

  • Page 109

    ... Freescale Semiconductor, Inc. In Table 7-5, the following notation applies: An — Address register operand Dn — Data register operand ea — An operand specified by an effective address M — Memory effective address operand Table 7-5. Standard Instruction Execution Times Instruction Size ADD/ADDA Byte Word Long AND ...

  • Page 110

    ... Freescale Semiconductor, Inc. shown in the previously described format. The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). In Table 7-6, the following notation applies: # — Immediate operand Dn — ...

  • Page 111

    ... Freescale Semiconductor, Inc. Table 7-7. Single Operand Instruction Instruction CLR NBCD NEG NEGX NOT Scc TAS TST +Add effective address calculation time. 7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES Table 7-8 lists the timing data for the shift and rotate instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 112

    ... Freescale Semiconductor, Inc. 7.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table 7-9 lists the timing data for the bit manipulation instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+) ...

  • Page 113

    ... Freescale Semiconductor, Inc. 7.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES Table 7-11 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective address (LEA), push effective address (PEA), and move multiple registers (MOVEM) instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 114

    ... Freescale Semiconductor, Inc. Table 7-12. Multiprecision Instruction Instruction ADDX CMPM SUBX ABCD SBCD 7.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Tables 7-13 and 7-14 list the timing data for miscellaneous instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 115

    ... Freescale Semiconductor, Inc. Table 7-13. Miscellaneous Instruction Execution Times Instruction ANDI to CCR ANDI to SR EORI to CCR EORI to SR EXG EXT LINK MOVE to CCR MOVE to SR MOVE from SR MOVE to USP MOVE from USP NOP ORI to CCR ORI to SR RESET RTE RTR RTS ...

  • Page 116

    ... Freescale Semiconductor, Inc. periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). Table 7-15. Exception Processing Address Error Bus Error CHK Instruction Divide by Zero Interrupt Illegal Instruction ...

  • Page 117

    ... Freescale Semiconductor, Inc. SECTION 8 16-BIT INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock (CLK) periods for the MC68000, MC68HC000, MC68HC001, and the MC68EC000 in 16- bit mode. In this data assumed that both memory read and write cycles consist of four clock periods ...

  • Page 118

    ... Freescale Semiconductor, Inc. Table 8-1. Effective Address Calculation Times Addressing Mode Dn Data Register Direct An Address Register Direct (An) Address Register Indirect (An)+ Address Register Indirect with Postincrement –(An) Address Register Indirect with Predecrement ( An) Address Register Indirect with Displacement ( An, Xn)* Address Register Indirect with Index (xxx) ...

  • Page 119

    ... Freescale Semiconductor, Inc. Table 8-3. Move Long Instruction Execution Times Source Dn An (An) Dn 4(1/0) 4(1/0) 12(1/2) An 4(1/0) 4(1/0) 12(1/2) (An) 12(3/0) 12(3/0) 20(3/2) (An)+ 12(3/0) 12(3/0) 20(3/2) –(An) 14(3/0) 14(3/0) 22(3/ An) 16(4/0) 16(4/0) 24(4/ An, Xn)* 18(4/0) 18(4/0) 26(4/2) (xxx).W 16(4/0) 16(4/0) 24(4/2) (xxx).L ...

  • Page 120

    ... Freescale Semiconductor, Inc. Table 8-4. Standard Instruction Execution Times Instruction Size ADD/ADDA Byte, Word Long AND Byte, Word Long CMP/CMPA Byte, Word Long DIVS DIVU EOR Byte, Word Long MULS MULU OR Byte, Word Long SUB Byte, Word Long + Add effective address calculation time. ...

  • Page 121

    ... Freescale Semiconductor, Inc. Table 8-5. Immediate Instruction Execution Times Instruction Size ADDI Byte, Word Long ADDQ Byte, Word Long ANDI Byte, Word Long CMPI Byte, Word Long EORI Byte, Word Long MOVEQ Long ORI Byte, Word Long SUBI Byte, Word Long ...

  • Page 122

    ... Freescale Semiconductor, Inc. Table 8-6. Single Operand Instruction Instruction CLR NBCD NEG NEGX NOT Scc TAS TST +Add effective address calculation time. 8.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES Table 8-7 lists the timing data for the shift and rotate instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 123

    ... Freescale Semiconductor, Inc. 8.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table 8-8 lists the timing data for the bit manipulation instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+) ...

  • Page 124

    ... Freescale Semiconductor, Inc. 8.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES Table 8-10 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective address (LEA), push effective address (PEA), and move multiple registers (MOVEM) instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 125

    ... Freescale Semiconductor, Inc. Table 8-11. Multiprecision Instruction Instruction ADDX CMPM SUBX ABCD SBCD 8.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Tables 8-12 and 8-13 list the timing data for miscellaneous instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 126

    ... Freescale Semiconductor, Inc. Table 8-12. Miscellaneous Instruction Execution Times Instruction ANDI to CCR ANDI to SR CHK (No Trap) EORI to CCR EORI to SR ORI to CCR ORI to SR MOVE from SR MOVE to CCR MOVE to SR EXG EXT LINK MOVE from USP MOVE to USP NOP RESET RTE ...

  • Page 127

    ... Freescale Semiconductor, Inc. the handler routine. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+) ...

  • Page 128

    ... Freescale Semiconductor, Inc. SECTION 9 MC68010 INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock (CLK) periods for the MC68010. In this data assumed that both memory read and write cycles consist of four clock periods. A longer memory cycle causes the generation of wait states that must be added to the total instruction times ...

  • Page 129

    ... Freescale Semiconductor, Inc. 9.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES Table 9-1 lists the numbers of clock periods required to compute the effective addresses for instructions. The totals include fetching any extension words, computing the address, and fetching the memory operand. The total number of clock periods, the number of read cycles, and the number of write cycles (zero for all effective address calculations) are shown in the previously described format ...

  • Page 130

    ... Freescale Semiconductor, Inc. Table 9-2. Move Byte and Word Instruction Execution Times Source Dn An (An) Dn 4(1/0) 4(1/0) 8(1/1) An 4(1/0) 4(1/0) 8(1/1) (An) 8(2/0) 8(2/0) 12(2/1) (An)+ 8(2/0) 8(2/0) 12(2/1) –(An) 10(2/0) 10(2/0) 14(2/ An) 12(3/0) 12(3/0) 16(3/ An, Xn)* 14(3/0) 14(3/0) 18(3/1) (xxx).W 12(3/0) 12(3/0) 16(3/1) (xxx) ...

  • Page 131

    ... Freescale Semiconductor, Inc. Table 9-4. Move Long Instruction Execution Times Source Dn An (An) Dn 4(1/0) 4(1/0) 12(1/2) An 4(1/0) 4(1/0) 12(1/2) (An) 12(3/0) 12(3/0) 20(3/2) (An)+ 12(3/0) 12(3/0) 20(3/2) –(An) 14(3/0) 14(3/0) 22(3/ An) 16(4/0) 16(4/0) 24(4/ An, Xn)* 18(4/0) 18(4/0) 26(4/2) (xxx).W 16(4/0) 16(4/0) 24(4/2) (xxx).L ...

  • Page 132

    ... Freescale Semiconductor, Inc. Table 9-6. Standard Instruction Execution Times Instruction Size ADD/ADDA Byte, Word Long AND Byte, Word Long CMP/CMPA Byte, Word Long DIVS DIVU EOR Byte, Word Long MULS/MULU OR Byte, Word Long SUB/SUBA Byte, Word Long + Add effective address calculation time. ...

  • Page 133

    ... Freescale Semiconductor, Inc. 9.4 IMMEDIATE INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in Table 9-8 include the times to fetch immediate operands, perform the operations, store the results, and read the next operation. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 134

    ... Freescale Semiconductor, Inc. Table 9-9. Single Operand Instruction Instruction NBCD NEG NEGX NOT Scc TAS TST +Add effective address calculation time. *Use nonfetching effective address calculation time. Table 9-10. Clear Instruction Execution Times Size Dn An CLR Byte, Word 4(1/0) — Long 6(1/0) — ...

  • Page 135

    ... Freescale Semiconductor, Inc. Table 9-11. Single Operand Instruction Loop Mode Execution Times Loop Continued Valid Count, cc False Instruction Size (An) (An)+ CLR Byte, 10(0/1) 10(0/1) Word Long 14(0/2) 14(0/2) NBCD Byte 18(1/1) 18(1/1) NEG Byte, 16(1/1) 16(1/1) Word Long 24(2/2) 24(2/2) NEGX ...

  • Page 136

    ... Freescale Semiconductor, Inc. Table 9-13. Shift/Rotate Instruction Loop Mode Execution Times Loop Continued Valid Count cc False Instruction Size (An) (An)+ ASR, ASL Word 18(1/1) 18(1/1) LSR, LSL Word 18(1/1) 18(1/1) ROR, ROL Word 18(1/1) 18(1/1) ROXR, ROXL Word 18(1/1) 18(1/1) 9.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table 9-14 lists the timing data for the bit manipulation instructions ...

  • Page 137

    ... Freescale Semiconductor, Inc. Table 9-15. Conditional Instruction Execution Times Instruction Displacement Bcc BRA BSR DBcc 9.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES Table 9-16 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective address (LEA), push effective address (PEA), and move multiple registers (MOVEM) instructions ...

  • Page 138

    ... Freescale Semiconductor, Inc. and read the next instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. The following notation applies in Table 9-17: Dn — Data register operand M — Memory operand Table 9-17 ...

  • Page 139

    ... Freescale Semiconductor, Inc. Table 9-18. Miscellaneous Instruction Execution Times Instruction Size ANDI to CCR — ANDI to SR — CHK — EORI to CCR — EORI to SR — EXG — EXT Word Long LINK — MOVE from CCR — MOVE to CCR — MOVE from SR — ...

  • Page 140

    ... Freescale Semiconductor, Inc. 9.12 EXCEPTION PROCESSING EXECUTION TIMES Table 9-19 lists the timing data for exception processing. The numbers of clock periods include the times for all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format ...

  • Page 141

    ... Freescale Semiconductor, Inc. SECTION 10 ELECTRICAL AND THERMAL CHARACTERISTICS This section provides information on the maximum rating and thermal characteristics for the MC68000, MC68HC000, MC68HC001, MC68EC000, MC68008, and MC68010. 10.1 MAXIMUM RATINGS Rating Supply Voltage Input Voltage Maximum Operating Temperature Range Commerical Extended "C" Grade Commerical Extended " ...

  • Page 142

    ... Freescale Semiconductor, Inc. 10.3 POWER CONSIDERATIONS The average die-junction temperature can be obtained from +(P D • where Ambient Temperature Package Thermal Resistance, Junction-to-Ambient, C INT + P I/O P INT = Watts — Chip Internal Power P I/O = Power Dissipation on Input and Output Pins — User Determined For most applications, P I/O <P INT and can be neglected. ...

  • Page 143

    ... Freescale Semiconductor, Inc. Table 10-1 summarizes maximum power dissipation and average junction temperature for the curve drawn in Figure 10-1, using the minimum and maximum values of ambient temperature for different packages and substituting J C for J A (assuming good thermal management). Table 10-2 provides the maximum power dissipation and average junction temperature assuming that no thermal management is applied (i ...

  • Page 144

    ... Freescale Semiconductor, Inc. Table 10-1. Power Dissipation and Junction Temperature vs Temperature Package T A Range NOTE: Table does not include values for the MC68000 12F. Does not apply to the MC68HC000, MC68HC001, and MC68EC000. Table 10-2. Power Dissipation and Junction Temperature vs Temperature ...

  • Page 145

    ... Freescale Semiconductor, Inc. is lost through the active P-channel transistor. Also, since only one transistor is turned on during the steady state, power consumption is determined by leakage currents. Because the basic CMOS cell is composed of two complementary transistors, a virtual semiconductor controlled rectifier (SCR) may be formed when an input exceeds the supply voltage ...

  • Page 146

    ... Freescale Semiconductor, Inc. 1.5 V BCLK DRIVE TO 0.5 V VALID OUTPUTS(1) OUTPUT n DRIVE TO INPUTS(2) DRIVE TO RSTI (3) NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This input timing is applicable to all parameters specified relative to the rising edge of the clock. ...

  • Page 147

    ... Freescale Semiconductor, Inc. 10.6 MC68000/68008/68010 DC ELECTRICAL CHARACTERISTICS (V CC =5.0 VDC 5%; GND=0 VDC Characteristic Input High Voltage Input Low Voltage Input Leakage Current BERR , BGACK DTACK, CLK, IPL0—IPL2, VPA @ 5.25 V Three-State (Off State) Input Current @ 2.4 V/0.4 V Output High Voltage ( –400 A) ...

  • Page 148

    ... Freescale Semiconductor, Inc. 10.7 DC ELECTRICAL CHARACTERISTICS (Applies To All Processors Except The MC68EC000) H Characteristic Input High Voltage Input Low Voltage Input Leakage Current BERR , BGACK DTACK, CLK, IPL0—IPL2, VPA @ 5.25 V Three-State (Off State) Input Current @ 2.4 V/0.4 V Output High Voltage Output Low Voltage ( ...

  • Page 149

    ... Freescale Semiconductor, Inc. 10.9 MC68008 AC ELECTRICAL SPECIFICATIONS — CLOCK TIMING Figure 10-3) Num Characteristic Frequency of Operation 1 Cycle Time 2,3 Clock Pulse Width 4,5 Clock Rise and Fall Times *These specifications represent an improvement over previously published specifications for the 8-, and 10-MHz MC68008 and are valid only for product bearing date codes of 8827 and later 2 ...

  • Page 150

    ... Freescale Semiconductor, Inc. 10.10 AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (V CC =5.0 VDC 5+; GND (see Figures 10-4 and 10-5) (Applies To All Processors Except The MC68EC000) Num Characteristic 6 Clock Low to Address Valid 6A Clock High to FC Valid 7 Clock High to Address, Data Bus High Impedance ...

  • Page 151

    ... Freescale Semiconductor, Inc. Num Characteristic 2 26 Data-Out Valid to DS Asserted (Write Data-In Valid to Clock Low (Setup Time on Read) 5 27A Late BERR Asserted to Clock Low (setup Time AS, DS Negated to DTACK Negated (Asynchronous Hold) 28A AS, DS Negated to Data-In High Impedance 29 AS, DS Negated to Data-In ...

  • Page 152

    ... Freescale Semiconductor, Inc. Num Characteristic 5 47 Asynchronous Input Setup Time BERR Asserted to DTACK Asserted 2,3,5 48 DTACK Asserted to BERR Asserted (MC68010 Only AS, DS, Negated to E Low 50 E Width High 51 E Width Low 53 Data-Out Hold from Clock High 54 E Low to Data-Out Invalid Asserted to Data Bus ...

  • Page 153

    ... Freescale Semiconductor, Inc. S0 CLK FC2–FC0 A23– LDS / UDS 17 R/W DTACK DATA IN BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the next falling edge of the clock need fall at this time only to insure being recognized at the end of the bus cycle. ...

  • Page 154

    ... Freescale Semiconductor, Inc. S0 CLK FC2-FC0 A23- LDS / UDS 17 R/W DTACK 7 DATA OUT BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 ...

  • Page 155

    ... Freescale Semiconductor, Inc. 10.11 AC ELECTRICAL SPECIFICATIONS—MC68000 TO M6800 PERIPHERAL (V CC (Applies To All Processors Except The MC68EC000) Num Characteristic 12 1 Clock Low to AS, DS Negated 18 1 Clock High to R/W High (Read Clock High to R/W Low (Write) 23 Clock Low to Data-Out Valid (Write) 27 Data-In Valid to Clock Low ...

  • Page 156

    ... Freescale Semiconductor, Inc CLK A23- R VPA VMA DATA OUT DATA IN NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the best case possible attainable Figure 10-6. MC68000 to M6800 Peripheral Timing Diagram (Best Case) (Applies Processors E xcept The MC68EC 000) ...

  • Page 157

    ... Freescale Semiconductor, Inc. 10.12 AC ELECTRICAL SPECIFICATIONS — BUS ARBITRATION VDC 5%; GND=0 VDC See Figure s 10-7 – 10-11) (Applies To All Processors Except The MC68EC000) Num Characteristic 7 Clock High to Address, Data Bus High Impedance (Maximum) 16 Clock High to Control Bus High Impedance 33 Clock High to BG Asserted ...

  • Page 158

    ... Freescale Semiconductor, Inc. STROBES AND R/W BR BGACK CLK NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, IPL2-IPL0, and VPA guarantees their recognition at the next falling edge of the clock. Figure 10-7. Bus Arbitration Timing (Applies Processors E xcept The MC68EC 000) ...

  • Page 159

    ... Freescale Semiconductor, Inc. CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure 10-8. Bus Arbitration Timing (A pplies rocessors E xcept The MC68EC 000) ...

  • Page 160

    ... Freescale Semiconductor, Inc. CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure 10-9. Bus Arbitration Timing — Idle Bus Case (Applies Processors E xcept The MC68EC 000) ...

  • Page 161

    ... Freescale Semiconductor, Inc. CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version Only. Figure 10-10. Bus Arbitration Timing — Active Bus Case (A pplies rocessors E xcept The MC68EC 000) ...

  • Page 162

    ... Freescale Semiconductor, Inc. CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure 10-11. Bus Arbitration Timing — Multiple Bus Request (Applies Processors E xcept The MC68EC 000) ...

  • Page 163

    ... Freescale Semiconductor, Inc. 10.13 MC68EC000 DC ELECTRICAL SPECIFICATIONS GND=0 VDC Characteristic Input High Voltage Input Low Voltage BERR DTACK , CLK, IPL2–IPL0, AVEC Input Leakage Current @5.25 V Three-State (Off State) Input Current @2.4 V/0.4 V Output High Voltage (I OH =–400 A) Output Low Voltage (IOL = 1 ...

  • Page 164

    ... Freescale Semiconductor, Inc. 10.14 MC68EC000 AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES 10-12 and 10-13) Num Characteristic 6 Clock Low to Address Valid 6A Clock High to FC Valid 7 Clock High to Address, Data Bus High Impedance (Maximum) 8 Clock High to Address, FC Invalid (Minimum Clock High Asserted ...

  • Page 165

    ... Freescale Semiconductor, Inc. Num Characteristic 29 AS, DS Negated to Data-In Invalid (Hold Time on Read) 29A AS, DS Negated to Data-In High Impedance 30 AS, DS Negated to BERR Negated DTACK Asserted to Data-In Valid (Setup Time) 32 HALT and RESET Input Transition Time 33 Clock High to BG Asserted 34 Clock High to BG Negated ...

  • Page 166

    ... Freescale Semiconductor, Inc. S0 CLK FC2–FC0 A23– LDS / UDS 17 R/W DTACK DATA IN BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the next falling edge of the clock need fall at this time only to insure being recognized at the end of the bus cycle. ...

  • Page 167

    ... Freescale Semiconductor, Inc. S0 CLK FC2-FC0 A23-A0 AS LDS / UDS R/W DTACK DATA OUT BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 ...

  • Page 168

    ... Freescale Semiconductor, Inc. 10.15 MC68EC000 AC ELECTRICAL SPECIFICATIONS—BUS ARBITRATION (VCC=5.0VDC Num Characteristic 7 Clock High to Address, Data Bus High Impedance (Maximum) 16 Clock High to Control Bus High Impedance 33 Clock High to BG Asserted 34 Clock High to BG Negated 35 BR Asserted to BG Asserted Negated to BG Negated ...

  • Page 169

    ... Freescale Semiconductor, Inc. CLK R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. Figure 10-14. MC68EC000 Bus Arbitration Timing Diagram MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, ...

  • Page 170

    ... Freescale Semiconductor, Inc. SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA This section provides pin assignments and package dimensions for the devices described in this manual. 11.1 PIN ASSIGNMENTS Package 64-Pin Dual-In-Line 68-Terminal Pin Grid Array 64-Lead Quad Pack 68-Lead Quad Flat Pack 52-Lead Quad ...

  • Page 171

    ... Freescale Semiconductor, Inc UDS LDS R/W DTACK BG BGACK CLK GND HALT RESET VMA VPA BERR IPL2 IPL1 IPL0 FC2 FC1 FC0 Figure 11-1. 64-Pin Dual In Line 11-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product MC68000 MC68010 16 49 ...

  • Page 172

    ... Freescale Semiconductor, Inc. MC68000/MC68010/MC68HC000 K NC FC2 FC0 BERR IPL0 FC1 IPL2 IPL1 G VMA VPA F (BOTTOM VIEW) HALT RESET E CLK GND BGACK BG R/W B DTACK LDS UDS Figure 11-2. 68-Lead Pin Grid Array MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, ...

  • Page 173

    ... Freescale Semiconductor, Inc. DTACK 10 BG BGACK CLK GND GND 18 NC HALT RESET VMA E VPA BERR IPL2 IPL1 26 R/W 10 DTACK BG BGACK CLK GND 18 GND MODE HALT RESET NC AVEC BERR IPL2 IPL1 26 Figure 11-3. 68-Lead Quad Pack ( 11-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

  • Page 174

    ... Freescale Semiconductor, Inc. DTACK 10 BG BGACK CLK GND GND 18 MODE HALT RESET VMA E VPA BERR IPL2 IPL1 26 Figure 11-3. 68-Lead Quad Pack ( A10 A11 A12 A13 A 21 A14 CC V A15 GND A16 A17 A18 20 Figure 11-4. 52-Lead Quad Pack MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

  • Page 175

    ... Freescale Semiconductor, Inc A10 A11 A12 A13 A14 V CC A15 GND A16 A17 A18 A19 Figure 11-5. 48-Pin Dual In Line 11-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product FC0 5 44 FC1 6 43 FC2 7 42 IPL2/IPL0 8 41 IPL1 ...

  • Page 176

    ... Freescale Semiconductor, Inc. 1 R/W DTACK CLK GND MODE HALT RESET AVEC BERR IPL2 IPL1 IPL0 FC2 16 Figure 11-6. 64-Lead Quad Flat Pack 11.2 PACKAGE DIMENSIONS Case Package 740-03 L Suffix 767-02 P Suffix 746-01 LC Suffix 754-01 R and P Suffix 765A-05 RC Suffix 778-02 FN Suffix 779-02 FN Suffix ...

  • Page 177

    ... Freescale Semiconductor, Inc NOTES: 1. DIMENSION -A- IS DATUM. 2. POSTIONAL TOLERANCE FOR LEADS: 0.25 (0.010 -T- IS SEATING PLANE 4. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5m, 1982. Figure 11-7. Case 740-03—L Suffix 11-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

  • Page 178

    ... Freescale Semiconductor, Inc NOTES: 1. -R- IS END OF PACKAGE DATUM PLANE -T- IS BOTH A DATUM AND SEATING PLANE 2. POSITIONAL TOLERANCE FOR LEADS 1 AND 48. 0.51 (0.020 POSITIONAL TOLERANCE FOR LEAD PATTERN; 0.25 (0.020 DIMENSION "A" AND "B" DOES NOT INCLUDE MOLD FLASH, MAXIMUM MOLD FLASH 0.25 (0.010). ...

  • Page 179

    ... Freescale Semiconductor, Inc NOTES: 1. DIMENSION -A- IS DATUM. 2. POSTIONAL TOLERANCE FOR LEADS: 0.25 (0.010 -T- IS SEATING PLANE 4. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5, 1973. Figure 11-9. Case 746-01—LC Suffix 11-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

  • Page 180

    ... Freescale Semiconductor, Inc NOTES: 1. DIMENSIONS A AND B ARE DATUMS. 2. -T- IS SEATING PLANE. 3. POSITIONAL TOLERANCE FOR LEADS (DIMENSION D): B 0.25 (0.010 DIMENSION B DOES NOT INCLUDEMOLD FLASH. 5. DIMENSION CENTER OF LEADS WHEN FORMED PARALLEL. 6. DIMENSIONING AND TOLERANCING PER ANSI Y14.5, 1982. Figure 11-10. Case 754-01—R and P Suffix ...

  • Page 181

    ... Freescale Semiconductor, Inc. Figure 11-11. Case 765A-05—RC Suffix 11-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

  • Page 182

    ... Freescale Semiconductor, Inc. APPENDIX A MC68010 LOOP MODE OPERATION In the loop mode of the MC68010, a single instruction is executed repeatedly under control of the test condition, decrement, and branch (DBcc) instruction without any instruction fetch bus cycles. The execution of a single-instruction loop without fetching an instruction provides a highly efficient means of repeating an instruction because the only bus cycles required are those that read and write the operands ...

  • Page 183

    ... Freescale Semiconductor, Inc. 1. Fetch the MOVE instruction. 2. Fetch the DBEQ instruction. 3. Read the operand at the address in A0. 4. Write the operand at the address in A1. 5. Fetch the displacement word of the DBEQ instruction. Of these five bus cycles, only two move the data. However, the MC68010 has a two-word prefetch queue in addition to the one-word instruction decode register ...

  • Page 184

    ... Freescale Semiconductor, Inc. Table A-1. MC68010 Loop Mode Instructions Opcodes MOVE [BWL] ADD [BWL] AND [BWL] CMP [BWL] OR [BWL] SUB [BWL] ADDA [WL] CMPA [WL] SUBA [WL] ADD [BWL] AND [BWL] EOR [BWL] OR [BWL] SUB [BWL] ABCD [B] ADDX [BWL] SBCD [B] SUBX [BWL] CMP [BWL] ...

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