MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 145

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

A block diagram of the CPU32+ is shown in Figure 5-1. The major blocks depicted operate
in a highly independent fashion that maximizes concurrences of operation while managing
the essential synchronization of instruction execution and bus operation. The bus controller
loads instructions from the data bus into the decode unit. The sequencer and control unit
provide overall chip control by managing the internal buses, registers, and functions of the
execution unit.
5.1.2 Loop Mode Instruction Execution
The CPU32+ has several features that provide efficient execution of program loops. One of
these features is the DBcc looping primitive instruction. To increase the performance of the
CPU32+, a loop mode has been added to the processor. The loop mode is used by any sin-
gle-word instruction that does not change the program flow. Loop mode is implemented in
conjunction with the DBcc instruction. Figure 5-2 shows the required form of an instruction
loop for the processor to enter loop mode.
The loop mode is entered when the DBcc instruction is executed and the loop displacement
is –4. Once in loop mode, the processor performs only the data cycles associated with the
instruction and suppresses all instruction fetches. The termination condition and count are
checked after each execution of the data operations of the looped instruction. The CPU32+
automatically exits the loop mode during interrupts or other exceptions.
• Enhanced Breakpoint Instruction
• Trace on Change of Flow
• Table Lookup and Interpolate (TBL) Instruction
• LPSTOP Instruction
• Hardware BKPT Signal, Background Mode
• Fully Static Implementation
DATA BUS
ADDRESS
BUS
16
32
Freescale Semiconductor, Inc.
For More Information On This Product,
SEQUENCER
EXECUTION
Figure 5-1. CPU32+ Block Diagram
CONTROL
UNIT
UNIT
MC68360 USER’S MANUAL
Go to: www.freescale.com
INSTRUCTION
PREFETCH
CONTROL
DECODE
AND
BUS
BUS CONTROL
CPU32+