MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 356

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
IDMA channel will terminate the transfer of a block of memory if this register reaches zero
during operation.
7.6.2.7 CHANNEL STATUS REGISTER (CSR). The CSR is an 8-bit register used to report
events recognized by the IDMA controller. On recognition of an event, the IDMA sets its cor-
responding bit in the CSR, regardless of the corresponding bits in the CMAR. The CSR is a
memory-mapped register that may be read at any time. A bit is reset by writing a one and is
left unchanged by writing a zero. More than one bit may be reset at a time, and the register
is cleared by reset.
Bits 7–6—Reserved
AD—Auxiliary Done
BRKP—Breakpoint
OB—Out of Buffers
BES—Bus Error Source
BED—Bus Error Destination
DONE—Normal Channel Transfer Done
7-32
This bit is valid in auto buffer and buffer chaining modes. It is set when the IDMA channel
has completed a buffer transfer for a buffer descriptor (BD) that has its I-bit set. For AD to
be set, the BCR must have been decremented to zero with no errors occurring during any
IDMA transfer bus cycle. The IDMA will then move to the next BD and continue to transfer
data.
This bit indicates that the breakpoint signal was asserted during an IDMA transfer. This
bit is cleared by writing a one or by reset. Writing a zero has no effect on BRKP.
This bit is valid only when the RISC controls the IDMA (RCI bit in the CMR is set). It is set
when working with the RISC controller and there are no more valid buffers out of which to
transfer data.
This bit indicates that the IDMA channel terminated with an error during the read cycle.
The channel terminates the IDMA operation without setting DONE. BES is cleared by writ-
ing a one or by setting RST in the CMR. Writing a zero has no effect on BES.
This bit indicates that the IDMA channel terminated with an error during the write cycle.
The channel terminates the IDMA operation without setting DONE. BED is cleared by writ-
ing a one or by setting RST in the CMR. Writing a zero has no effect on BED.
This bit indicates that the IDMA channel has terminated normally. Normal channel termi-
nation is defined as follows:
1. In single buffer mode, the BCR has decremented to zero, and no errors have
occurred during any IDMA transfer bus cycle.
Freescale Semiconductor, Inc.
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AD
5
BRKP
4
OB
3
BES
2
BED
1
DONE
0