MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 256

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
The PIT does not respond to an LPSTOP instruction; thus, it can be used to exit LPSTOP
as long as the interrupt request level is higher than the CPU32+ interrupt mask level. To stop
the PIT while in LPSTOP, the PITR must be loaded with a zero value before LPSTOP is exe-
cuted. The bus monitor, double bus fault monitor, and spurious interrupt monitor are all inac-
tive during LPSTOP.
If an external device requires additional time to prepare for entry into LPSTOP mode, entry
can be delayed by asserting HALT (see 4.4.2 LPSTOP Broadcast Cycle).
6.4 LOW POWER IN NORMAL OPERATION
In addition to the LPSTOP mode, the SIM60 supports methods to minimize power consump-
tion in normal operation. In normal operation, the QUICC provides several options to reduce
power consumption:
The SIM60 also supports methods to reduce power by dividing the clocks internally. This is
called slow-go mode and is described in 6.5 SIM60 System Clock Generation.
6.5 SIM60 SYSTEM CLOCK GENERATION
The QUICC has an on-chip oscillator, a clock synthesizer, and a low-power divider, which
allow a comprehensive set of choices in generating system clocks (see Figure 6-5). The
choices offer many opportunities to save power and system cost, without sacrificing flexibil-
ity and control.
The operation of the clocks is determined by three registers: the clock out control register
(CLKOCR), the phase-locked loop control register (PLLCR), and the clock divider control
register (CDVCR). Each register has a protection mechanism to prevent accidental writing.
The clock generation features are discussed in the following paragraphs.
6.5.1 Clock Generation Methods
The first method drives the system clock at the desired system frequency (10–25 MHz),
directly onto the EXTAL pin. A second method drives the EXTAL pin with a selected fre-
quency which is pre-scaled and multiplied by the PLL. With these two methods, the XTAL
pin should be left floating. A third method uses a reference crystal frequency which can also
be pre-scaled and multiplied. This can be any frequency from 25 kHz to 6.0 MHz. Figure 6-
6 shows external connections required for the on-chip oscillator as well as the other clock-
related V
6-12
• The sub-block clock generators are automatically disabled when the sub-block is not
• In most of the IMB sub-modules, there is a bit (e.g., STOP or RESET), that can disable
active. For example, when the RISC controller is idle (no pending request is present
from the serial channels), its clock generator is automatically stopped.
the clock generator in that module (except for its IMB interface unit).
CC
and GND connections.
The IDMA channels should be disabled prior to issuing the LP-
STOP instruction.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE