MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 588

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MC68MH360AI33L

Manufacturer Part Number
MC68MH360AI33L
Description
IC MPU QUICC 33MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360AI33L

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68MH360AI33L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Serial Communication Controllers (SCCs)
7.10.23.20 ETHERNET EVENT REGISTER (SCCE). The SCCE is called the Ethernet
event register when the SCC is operating as an Ethernet controller. It is a 16-bit register
used to report events recognized by the Ethernet channel and to generate interrupts. On
recognition of an event, the Ethernet controller will set the corresponding bit in the Ethernet
event register. Interrupts generated by this register may be masked in the Ethernet mask
register. An example of interrupts that may be generated in the HDLC protocol is given in
Figure 7-72.
The Ethernet event register is a memory-mapped register that may be read at any time. A
bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
Bits 15–8, 6–5—Reserved
GRA—Graceful Stop Complete
TXE—Tx Error
RXF—Rx Frame
BSY—Busy Condition
TXB—Tx Buffer
RXB—Rx Buffer
7-264
15
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any frame
that was in progress when the command was issued. It will be set immediately if no frame
was in progress when the command was issued.
An error occurred on the transmitter channel.
A complete frame was received on the Ethernet channel.
A frame was received and discarded due to lack of buffers.
A buffer has been transmitted on the Ethernet channel.
A buffer that was not a complete frame has been received on the Ethernet channel.
14
13
12
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Freescale Semiconductor, Inc.
For More Information On This Product,
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
8
GRA
7
6
5
TXE
4
RXF
3
BSY
2
TXB
1
RXB
0

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