MC68360CRC25L Freescale Semiconductor, MC68360CRC25L Datasheet - Page 138

• Manufacturer Part Number: MC68360CRC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CRC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
Bus Operation
4.6.8 Show Cycles
The QUICC can perform data transfers with its internal modules without using the external
bus, but when debugging, it is desirable to have address and data information appear on the
external bus. These external bus cycles, called show cycles, are distinguished by the fact
that AS is not asserted externally. DS is used to signal address strobe timing in show cycles.
After reset, show cycles are disabled and must be enabled by writing to the SHEN bits in the
module configuration register. When show cycles are disabled, the address bus, function
codes, size, and read/write signals continue to reflect internal bus activity. However, AS and
DS are not asserted externally, and the external data bus remains in a high impedance
state. When show cycles are enabled, DS indicates address strobe timing and the external
data bus contains data. The following paragraphs are a state-by-state description of show
cycles, and Figure 4-45 illustrates a show cycle timing diagram. Refer to Section 10 Electri-
cal Characteristics for specific timing information.
State 0 – During state 0, the address and function codes become valid, R/W is driven to indi-
cate a show read or write cycle, and the size pins indicate the number of bytes to transfer.
During a read, the addressed peripheral is driving the data bus, and the user must take care
to avoid bus conflicts.
State 41 – One-half clock cycle later, DS (rather than AS) is asserted to indicate that address
information is valid.
State 42– No action occurs in state 42. The bus controller remains in state 42 (wait states
will be inserted) until the internal read cycle is complete.
State 43– When DS is negated, show data is valid on the next falling edge of the system
clock. The external data bus drivers are enabled so that data becomes valid on the external
bus as soon as it is available on the internal bus.
State 0 – The address, function codes, read/write, and size pins change to begin the next
cycle. Data from the preceding cycle is valid through state 0.
4-62
MC68360 USER’S MANUAL
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