MC68360CRC25L Freescale Semiconductor, MC68360CRC25L Datasheet - Page 203

• Manufacturer Part Number: MC68360CRC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CRC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM
remains enabled until the next system reset. A high BKPT on the trailing edge of RESET
disables BDM. BKPT is relatched on each rising transition of RESET. BKPT is synchronized
internally and must be held low for at least two clock(four clocks for RESETS)cycles prior to
negation of RESETH.
BDM enable logic must be designed with special care. If hold time on BKPT (after the trailing
edge of RESET) extends into the first bus cycle following reset, this bus cycle could be
tagged with a breakpoint. Refer to Section 4 Bus Operation for timing information.
5.6.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the tran-
sition from normal mode to BDM. These sources include external BKPT hardware, the
BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not
enabled when an exception condition occurs, the exception is processed normally. Table 5-
19 summarizes the processing of each source for both enabled and disabled cases. Note
that the BKPT instruction never causes a transition into BDM.
MICROCODE
EXECUTION
UNIT
BKPT
Double Bus Fault
BGND Instruction
BKPT Instruction
Source
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For More Information On This Product,
Table 5-19. BDM Source Summary
Figure 5-20. BDM Block Diagram
BERR
BKPT
IRC
SEQUENCER
MC68360 USER’S MANUAL
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Background
Background
Background
Opcode Substitution/
Illegal Instruction
BERR
BKPT
IRB
BDM Enabled
INTERFACE
SERIAL
BERR
BKPT
IR
Breakpoint Exception
Halted
Illegal Instruction
Opcode Substitution/
Illegal Instruction
CONTROL
BUS
BDM Disabled
IPIPE/DSO
IFETCH/DSI
BKPT/DSCLK
DATA BUS
BERR
FREEZE
ADDRESS BUS
CPU32+