MC68360CRC25L Freescale Semiconductor, MC68360CRC25L Datasheet - Page 573

• Manufacturer Part Number: MC68360CRC25L
• Description: IC MPU QUICC 25MHZ 241-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CRC25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

(according to the PAD bit in the Tx BD and the PAD value in the parameter RAM). PADs will
be added to make the transmit frame MINFLR bytes in length.
MAXD1. This parameter gives the user the ability to stop system bus writes from occurring
after a frame has exceeded a certain size. The value of this register is valid only if an
address match was detected. The Ethernet controller checks the length of an incoming
Ethernet frame against the user-defined value given in this 16-bit register. Typically, this reg-
ister is set to 1518 decimal. If this limit is exceeded, the remainder of the incoming frame is
discarded. The Ethernet controller waits to the end of the frame (or until MFLR bytes have
been received) and reports the frame status and the frame length in the last Rx BD.
MAXD2. This parameter gives the user the ability to stop system bus writes from occurring
after a frame has exceeded a certain size. The value of this register is valid in promiscuous
mode when no address match was detected. The Ethernet controller checks the length of
an incoming Ethernet frame against the user-defined value given in this 16-bit register. Typ-
ically, this register is set to 1518 decimal. If this limit is exceeded, the remainder of the
incoming frame is discarded. The Ethernet controller waits to the end of the frame (or until
MFLR bytes have been received) and reports the frame status and the frame length in the
last Rx BD.
In a monitor station, MAXD2 can be programmed to a value much less than MAXD1 to
receive entire frames addressed to this station, but receive only the headers of all other
frames.
GADDR1–4. These four registers are used in the hash table function of the group address-
ing mode. The user may write zeros to these values after reset and before the Ethernet
channel is enabled to disable all group hash address recognition functions. The SET
GROUP ADDRESS command is used to enable the hash table.
PADDR1. The user writes the 48-bit individual address of this station into this location.
PADDR1_L is the lowest order word, and PADDR1_H is the highest order word.
P_Per. This parameter allows the Ethernet controller to be less aggressive in its behavior
following a collision. Normally, this parameter should be set to $0000. To decrease the
aggressiveness of the Ethernet controller, P_Per can be set to a value from 1 to 9, with 9
being the least aggressive. The P_Per value is added to the retry count in the backoff algo-
rithm to reduce the probability of transmission on the next time slot.
The use of P_Per is fully allowed within Ethernet/802.3 specifi-
cations. In a heavily congested Ethernet LAN, a less aggressive
backoff algorithm used by multiple stations on the LAN increas-
es the overall LAN throughput by reducing the probability of col-
lisions.
The SBT bit in the PSMR offers another way to reduce the ag-
gressiveness of the Ethernet controller.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Communication Controllers (SCCs)